Transcript Memory Timing

dom Access Memory (RAM) Technol
• Why do computer designers
need to know about RAM
technology?
– Processor performance is
usually limited by memory
bandwidth
– As IC densities increase, lots
of memory will fit on
processor chip
• Tailor on-chip memory to
specific needs
- Instruction cache
- Data cache
- Write buffer
Memory Speed
Unit
one billionth of a second (
nanosecond)
DRAM: 50-100ns
SRAM: 10-50ns
ROM: 50-250ns
» CAS or Column Access Strobe
» RAS or Row Access Strobe
– Addresses divided into 2 halves (Memory as a 2D matrix):
– Dynamic since needs to be refreshed periodically (8 ms, 1% time)
• Main Memory is DRAM: Dynamic Random Access Memory
Cost/Cycle time: SRAM/DRAM - 8-16
Size: DRAM/SRAM - 4-8,
– No refresh (6 transistors/bit vs. 1 transistor
• Cache uses SRAM: Static Random Access Memory
– Low Level Architectures (FPM,EDO,BEDO,SDRAM)
– Physical Makeup (CMOS, DRAM)
• Different flavors at different levels
• Random Access Memory (vs. Serial Access Memory)
Main Memory Background
Timing Diagram
Conventions
Input Signal
Output Signal
Must be steady
high or low
Will be steady high or low
High-to-low
changes permitted
designated interval
Will be changing from
high-to-low during
Low-to high
changes permitted
designated interval
Will be changing from
low-to-high during
Don't-Care
State changing
(Does not apply)
Centerline represents high
impedance (off) state
RAM Timing
WE
Simplified Read Timing
Access Time
The time it takes for
new data to be ready
to appear at the
output
CS
Address
Valid Address
Access Time
Data Out
Data Out
WE
Simplified Write Timing
CS
Memory Cycle Time
Address
Valid Address
Data In
Input Data
The Clock Cycle
The most important parameter
of the clock is the duration of a cycle,
tCYC.
Valid Address
The old address is removed
in clock state S0 and the
address bus floated
Address Bus
Initially, in state
S0 the address
bus contains the
old address
In state S1 a new
address becomes
valid for the remainder
of the memory access
Valid Address
tCLAV
We
are interested in the relationship between the
time at which the address is valid and the time at
which the address strobe, AS*, is asserted
When AS*
is active-low it indicates that the address
is valid
We
now look at the timing of the clock, the address,
and the address strobe
AS* goes active low after
AS* goes inactive
the address has become valid
high before the address
changes
AS* goes low in clock
state S2
The
timing of DS* in a read cycle is the
same as the address strobe, AS*
The data strobe, is asserted
at the same time as AS*
in a read cycle
Data from the memory
appears near the end of
the read cycle
The earliest time at which the memory can
begin to access data is measured from the point
at which the address is first valid
Data from the memory is latched into
the 68000 by the falling edge of the
clock in state S6.
Data must be valid
tDICL seconds before
the falling edge of S6
We know that the time between the
address valid and data valid is tacc
The address becomes
valid tCLAV seconds after
the falling edge of S0
From the falling
edge of S0 to the
falling edge of S6:
•the address becomes valid
•the data is accessed
•the data is captured
3 tcyc = tCLAV + tacc + tDICL