Transcript WP2-2 and 2-3 - Indico

WP2: on-detector power
management
F.Faccio, G.Blanchot, S.Michelis,
S.Orlandi, C.Fuentes, B.Allongue
CERN – PH-ESE
1
Outline

Introduction
 Project structure




Technical status




Working Team
Communication
Composition of WP2
WP2-1
WP2-2 and 2-3
Resources
Conclusion
PH Theme 3 meeting
November 11, 2008
CERN - PH dept – ESE group
2
Distributing power
PS
No on-detector conversion. Low-voltage (2.5-5V) required by
electronics provided directly from off-detector. Sense wire
necessary for PS to provide correct voltage to electronics.
Patch Panels (passive connectors ensuring
current path between different cables.
Regulation is very seldom used)
Current path from PS to module (or more seldom star of modules) and return. Cables
get thinner approaching the collision point to be compatible with material budget.
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Distributing power
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Distributing power with DC-DC

The use of DC-DC converters allows the distribution of the
power at higher voltage, while the converters provide locally the
voltage level(s) required by the electronics
DC-DC principle
10xV, I
V, 10xI
DC-DC
Principle distribution scheme
1xI
10xV
I
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Challenges

Converters to be placed inside the tracker volume
Magnetic field (up to 4T)
Radiation field (>10Mrd)
Environment sensitive to noise
(EMI)

Commercial components are not designed for this radiation and
magnetic environment, we need a custom development (ASICs)
 Space is very limited, and requirements for low mass stringent. High
level of integration is mandatory
 Our goal: develop the ASICs necessary for the power distribution, and
help their integration in full detector systems
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Outline

Introduction
 Project structure




Technical status




Working Team
Communication
Composition of WP2
WP2-1
WP2-2 and 2-3
Resources
Conclusion
PH Theme 3 meeting
November 11, 2008
CERN - PH dept – ESE group
7
The team
Category
Working
time (%)
Comments
F.Faccio
Staff
40
G.Blanchot
Staff
30
B.Allongue
Staff
30
S.Michelis
MC fellow
100
Until 31/Oct/09
S.Orlandi
Fellow
100
Until 30/Jun/10
C.Fuentes
Upsa+HELEN
100
Doctoral from 1/feb/09 (EU
SLHC-PPfunds)
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Communication and coordination





In opposition to the early R&D phase of LHC, power distribution
is today very fashionable

3 Working Groups: ATLAS, CMS, “common”

CMS task force (first meeting today)

Separate sessions at TWEPP, ATLAS and CMS upgrade
workshops, ACES

SLHC-PP within FP7
Parallel activities on other distribution schemes (serial powering)
or different conversion approaches exist
Expectations of the community are high (and impatient – maybe
unnecessarily…)
This all puts the development under constant pressure – and
requires a very large amount of energy in reporting, coordination,
discussions, ….
Our activity is well known and reasonably well integrated in both
ATLAS and CMS – and improving
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Composition of WP2

Time frame: 3 years
Split of the project in 3 parts

WP2-1: Linear voltage regulation



WP2-2: DC-DC conversion (corresponding to SLHCPP deliverables)


Development of “stand-alone” component for low current
(100-300mA) applications
Development of converter prototype, integration in full-scale
detector modules
WP2-3: DC-DC conversion, Addition

Aspects and activities not covered by SLHC-PP
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Outline

Introduction
 Project structure




Technical status




Working Team
Communication
Composition of WP2
WP2-1
WP2-2 and 2-3
Resources
Conclusion
PH Theme 3 meeting
November 11, 2008
CERN - PH dept – ESE group
11
WP2-1: Status

Deliverables:
Component specifications
Report
31-Sep-08
Performance report on prototype
Prototype, Report
31-Mar-10
Full characterization, ready for series
production
Demonstrator
31-Mar-11


Progress:

Full schematic of the main regulation loop ready in IBM
130nm CMOS

Protection circuits (over-V, over-I, over-T) almost complete in
schematic
The component does not look to be really needed now. Much
more pressure on DC-DC development

To be discussed at technical committee meeting
(December?)
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WP2-2 and 2-3: deliverables

WP2-2 Deliverables (in parenthesis also WP2-3) :
Evaluation report on conversion technologies,
(including consultancy report)
Report
31-Mar-09
Prototypes of converters (and inductors) with
viability report, (CMOS qualification report)
Prototype, Report
31-Mar-10
Integration in full-scale detector modules
Demonstrator
31-Mar-11

Specific Additions in WP2-3

Consultancy to procure expertise in power electronics

Transformer based on piezoelectric ceramic materials

Second source CMOS technology

Optimization of air-core inductor
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Evaluation of conversion
technologies

Consultancy relationship established with PEL (Power
Electronics Labs), University of Padova

This collaboration proved extremely valuable

2 reports already produced. Design of 2 converters executed
and first prototype manufactured
• Comparison of 5 different converter topologies taylored for our
specific application. Choice restricted to 2 topologies (simple
buck and 2-phase interleaved buck with voltage divider)
• Results from the measurements of the 2 converter prototypes
(discrete components)

4 common working sessions organized: 2 in Padova and 2 at
CERN (2-3 days each)
• Extremely efficient form of transfer of knowledge
• Large progresses in the project

Outcome: we proposed at TWEPP a power distribution scheme
for SLHC trackers
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Proposed power distribution
scheme
Rod/stave
10-12V
If Ihybrid << Iout_converter
If Ihybrid ~ Iout_converter
Optoelectronics
1.8V
2.5V
Detector
2.5V
Detector
2.5V
Converter
stage 1
2 Converter stage 2 on-chip
Detector
10-12V
Detector
2 Converter stage2 on-chip
1.8V
2.5V
1.8V
2.5V
1.8V
1.25V
Stave controller
Converter stage 2
10-12V
Converter
stage 1 onhybrid
10-12V
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Converter stage 1
on-stave
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Different converter topologies (1/3)
The following DC/DC step down converter topologies have been evaluated
and compared in view of our specific application.
1.
2.
Single phase synchronous buck converter
↑ Simple, small number of passive components
↓ Larger output ripple for same Cout
↓ RMS current limitation for inductor are output
capacitance
4 phase interleaved synchronous buck converter
↑ Complete cancellation of output ripple for a
conversion ratio of 4 (with small Cout)
↑ Smaller current in each inductor (compatible
with available commercial inductors)
↓ Large number of passive components
↓ More complex control circuitry
Vin
L1
Q2
Vin
Vout
Q1
Q1
Rload
Cout
L1
Q2
L2
Q3
Vout
Cout
Rload
Q4
L3
Q5
Q6
L4
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Q7
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Q8
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Different converter topologies (2/3)
Two phase interleaved synchronous buck
converter with integral voltage divider
↑ Complete cancellation of output ripple for
a conversion ration of 4 (with small Cout)
↑ Simpler control and smaller number of
passive components than 4 phase
interleaved
4.
Multi-resonant buck converter
↑ Very small switching losses (zero voltage
and zero current switching)
↓ To achieve resonance:
 Current waveforms have high RMS
value => large conductive losses =>
lower efficiency
 Voltage waveforms have high
peaks, possibly stressing the
technology beyond max Vdd
↓ Different loads require complete retuning of converter parameters
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ig
Q1
ir
Vg
C1
Lr
+
Cr vr
Q2
D1
C2
D2
Io
+
vo
Load
3.
17
Different converter topologies (3/3)
switched capacitor voltage divider
↑ rather simple, limited number of
passive components
↑ lack of inductor => good for radiated
noise and for compact design
↓ No regulation of the output voltage,
only integer division of the input
voltage
↓ Efficiency decreases with conversion
ratio (larger number of switches)
↑ Good solution for ratio = 2, for which
high efficiency can be achieved
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ig
Q1
ix
Vg
Cx
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+
vx
+
C1
Q2
Io
Q3
+
C2
Q4
vo
Load
5.
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Conversion stage 1: topology
Waveforms of the different topologies have been computed with Mathcad, and conversion losses
have been estimated for each of them in the same conditions:
Vin= 10V, Pout= 6W, Vout= 2.5V (step down ratio = 4), use of AMS 0.18um technology with
approximate formula to account for switching losses
Components needed
Efficiency
Topologies
Number
of Switches
Number
of Capacitors
Number of
Inductors
86
2
2
1
4 phase Interleaved Buck
88.3
8
2
4
2 phase Interleaved Buck + VD
89.7
4
3
2
Multiresonant Buck
82.5
1
4
2
2 Cascaded Switched Capacitor
87.3
8
7
0
Buck converter
The best compromise in terms of efficiency, number of components required, complexity and output
ripple is the 2 phase interleaved buck with integrated voltage divider.
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Implementation: conversion stage 1
The final result of our study is that, for the development of a unique ASIC conversion stage 1 for
both analog and digital power distribution, the best solution is:




2-phase interleaved buck with integrated voltage divider
Switching frequency = 1 MHz
On-resistance of switching transistors = 30 mW
The inductor can be chosen for the specific output current wished in the application, achieving
the efficiency estimated in the graphs below for the AMS 0.18 technology (Coilcraft RF 132
series inductors are used)
ANALOG, Vout=2.5V
800
90
700
600
88
500
86
400
84
300
82
200
80
100
78
0
0
1
2
3
4
Output current (A)
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5
6
Efficiency
92
800
Inductance
90
700
Efficiency (%)
92
Inductance (nH)
Efficiency (%)
DIGITAL, Vout=1.8V
600
88
500
86
400
84
300
82
200
80
100
78
0
0
1
2
3
4
5
6
Output current (A)
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Inductance (nH)

Implementation: conversion stage 2

Two converters to be embedded on each chip


Output current rather modest (20-200 mA)
Inductor-based converters not envisageable:
• With on-chip inductors (high ESR) the efficiency
would be extremely low
• The use of several discrete inductors per ASIC is
not desirable – already only for system
integration purposes

Vin
Q1
Q2
Switched capacitor converters more suitable
• Acting as voltage divider (÷2)
• They unfortunately do not provide regulation,
which must be relied on from conversion stage 1
• Achievable efficiency has been estimated, then
refined with a quick simulation in a 130nm
technology (use of I/O transistors)


Vout=Vin/2
Q3
Q4
gnd
Efficiency (Vin=1.8V, Vout=0.9V, Iload=166mA,
f=20MHz) = 93%
It should be pointed out that no study on the
optimization of this converter has been made –
one only topology, with one fixed frequency has
been studied (efficiency can be improved further
by decreasing the frequency, for instance).
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WP2-2 and 2-3: deliverables

WP2-2 Deliverables (in parenthesis also WP2-3) :
Evaluation report on conversion technologies,
(including consultancy report)
Report
31-Mar-09
Prototypes of converters (and inductors) with
viability report, (CMOS qualification report)
Prototype, Report
31-Mar-10
Integration in full-scale detector modules
Demonstrator
31-Mar-11

Specific Additions in WP2-3

Consultancy to procure expertise in power electronics

Transformer based on piezoelectric ceramic materials

Second source CMOS technology

Optimization of air-core inductor
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Prototype of converters

Several prototype converters using discrete
components have been manufactured


Main objective: study EMC
First integrated prototype developed and
manufactured in a CMOS 0.35um technology
with high-V module
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ASIC development

ASIC designer: Stefano Michelis
 Prototype for “conversion stage 1”
 First prototype designed and
manufactured in AMIS I3T80
technology
 Simple buck topology




Vin up to 10V
Vout=2.5V
Iout up to 1.5A
switching frequency 0.3-1.2 MHz

ASIC included main functions only
(switches, control circuitry)
 External compensation network,
reference voltage and sawtooth
generator required
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ASIC Prototype performance





ASIC mounted on a custom PCB (chip
on board)
Functionality is OK, it provides
regulated output at 2.5V for different
loads
Efficiency limited to 70% max.

Known limitations from the use of
vertical transistors with large Ron

Additional losses probably due to
“shoot-through” (verification
ongoing)
Noise performance very reasonable
Used already to power CMS endcap
tracker modules (RWTH Aachen)
Second version – more complete and
with different power transistors – to be
submitted at the beginning of December
12
10
8
6
Voltage (V)

4
2
0
-2
-6
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Vin
Vind
Vout
-4
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-1
-0.5
0
time (s)
0.5
1
-6
x 10
25
WP2-2 and 2-3: deliverables

WP2-2 Deliverables (in parenthesis also WP2-3) :
Evaluation report on conversion technologies,
(including consultancy report)
Report
31-Mar-09
Prototypes of converters (and inductors) with
viability report, (CMOS qualification report)
Prototype, Report
31-Mar-10
Integration in full-scale detector modules
Demonstrator
31-Mar-11

Specific Additions in WP2-3

Consultancy to procure expertise in power electronics

Transformer based on piezoelectric ceramic materials

Second source CMOS technology

Optimization of air-core inductor
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CMOS technology

Full radiation characterization of AMIS IT380 technology (0.35um CMOS)
completed



Contacts established, in synergy with WP1, with two alternative providers



STM, possibly interested to a common development. 2 of their technologies
selected, samples provided. Samples are being irradiated now
AMS, developing a new 0.18um high-V CMOS technoloogy with IBM.
Participation in first MPW confirmed, but delayed by 6 months to 4/09
Contacts established with another alternative supplier, IHP





Report available
Performance not really matching requirements
Contact established via CNM Barcelona (ATLAS), now in coordinated way with
RTWH Aachen (CMS)
Provided samples are being irradiated now
IHP willing to collaborate in enhancing and maintaining radiation hardness
Design of test chip in collaboration with CNM and IHP is in progress
Objective: select one technology with appropriate characteristics, and move ASIC
prototyping in that technology as soon as possible
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WP2-2 and 2-3: deliverables

WP2-2 Deliverables (in parenthesis also WP2-3) :
Evaluation report on conversion technologies,
(including consultancy report)
Report
31-Mar-09
Prototypes of converters (and inductors) with
viability report, (CMOS qualification report)
Prototype, Report
31-Mar-10
Integration in full-scale detector modules
Demonstrator
31-Mar-11

Specific Additions in WP2-3

Consultancy to procure expertise in power electronics

Transformer based on piezoelectric ceramic materials

Second source CMOS technology

Optimization of air-core inductor
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Optimization of air-core inductors

Inductors are crucial components for the converter





Air-core inductors have to be used since ferromagnetic
materials saturate in the high magnetic field of
CMS/ATLAS
Since the current flowing is not dc, they are emitters of
magnetic field. This can induce noise
Their parasitic resistance strongly influences efficiency
Simulation studies are made to compare magnetic
field and ESR of different inductor designs
After choice of design, prototypes have to be
manufactured

This will likely require establishing relationship with
industry (custom coil manufacturers), unless a planar
PCB solution is chosen
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Which inductor to use?



Air-core inductors can be manufactured in different configurations (planar, solenoidal,
thoroidal, ….) and a choice should be made
Value: reasonably limited in range 100-700nH
Equivalent resistance (ESR) determines converter efficiency to sensible extent
Planar (on PCB)
ESR~100mW
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Solenoidal
ESR~20-30mW
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Thoroidal
ESR~20-30mW
30
Air core solenoid
Not shielded
Shielded
Value @ 11mm
far from the solenoid:
5µT
18nT
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Air core toroid
Value @ 11mm far from the toroid:
6.6µT
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Example PCB Toroid
This PCB toroid was developed at Bristol,
Aknowledegment to David Cussans
Not shielded
Shielded
Value @ 11mm far from the toroid:
19µT
70nT
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WP2-2 and 2-3: deliverables

WP2-2 Deliverables (in parenthesis also WP2-3) :
Evaluation report on conversion technologies,
(including consultancy report)
Report
31-Mar-09
Prototypes of converters (and inductors) with
viability report, (CMOS qualification report)
Prototype, Report
31-Mar-10
Integration in full-scale detector modules
Demonstrator
31-Mar-11

Specific Additions in WP2-3

Consultancy to procure expertise in power electronics

Transformer based on piezoelectric ceramic materials

Second source CMOS technology

Optimization of air-core inductor
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34
Integration in detector modules

Main issues for integration: EMC and physical
space

EMC


Measurements of noise (conducted and
radiated) on converter prototypes
Module-level tests
• @ RWTH Aachen with CMS TEC modules
• @ CERN with TOTEM Si Strip modules
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Conducted noise measurement

Reference test bench developed
within ESE



Well defined measurement
methods for reproducible and
comparable results.
Independence from the system
and from the bulk power source.
Arrangement of cables, input and
output filter (LISN) around the
converter under test, all above a
ground plane.
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Noise measurement
on different CERN prototypes
All the measurement were made in these conditions: Vin=10V, Vout=2.5V, Iout=1A and f sw=1Mhz
Proto 1,2,3 were developed at CERN with the same controller. PCB layout and parasitic component choice was improved
Proto 4’s PCB was designed in Aachen and the ASIC (in the red spot) was designed at CERN
Proto1
~58dBµA
Proto3
~46dBµA
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~62dBµA
~51dBµA
Proto2
Proto4
37
Powering a detector module
TOTEM Front-End system supplied with DC-DC converters
Expose the front-end system to the
DC-DC converter conducted noise
(Common Mode and Differential Mode
currents)
VFAT #4
#4
VFAT
VFAT #3
#3
VFAT
channel #127
#127
channel
VFAT #2
#2
VFAT
VFAT #1
#1
VFAT
channel #0
#0
channel
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Nominal
noise
Proto #3 with
long cables
Proto #3
Proto #4
VFAT #1
1.76
1.76
2.00
1.81
VFAT #2
1.81
1.73
2.00
1.77
VFAT #3
1.68
1.62
1.69
1.55
VFAT #4
1.56
1.59
1.93
1.67
CERN - PH dept – ESE group
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WP2-2 and 2-3: deliverables

WP2-2 Deliverables (in parenthesis also WP2-3) :
Evaluation report on conversion technologies,
(including consultancy report)
Report
31-Mar-09
Prototypes of converters (and inductors) with
viability report, (CMOS qualification report)
Prototype, Report
31-Mar-10
Integration in full-scale detector modules
Demonstrator
31-Mar-11

Specific Additions in WP2-3

Consultancy to procure expertise in power electronics

Transformer based on piezoelectric ceramic materials

Second source CMOS technology

Optimization of air-core inductor
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39
Piezoelectric transformers

2-days workshop organized in April at CERN


Held with Limiel (Dk) – consultancy firm on piezoceramic materials and
(in particular) their applications
Nothing similar to what we would need exists – requirement for
developing both the custom ceramic device AND the driving circuitry
• No on-field reliability data exist!!

Further difficulties emerged during the workshop
• Need for an output rectifier (difficult to achieve high efficiency for low
voltage)
• Since the capacitance of the transformer has to be matched to the load,
its size gets unpractical in our application (several cm per side, very
thin)
• The transformer can not cope with sudden output open – too much
energy stored that can not be dissipated. This is a safety concern

Conclusions



It looks very unlikely that an attractive solution for our application can be
found
In any case, an activity aimed purely at demonstrating the feasibility of
such very innovative approach would require our full resources
We decided to abandon this solution
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Outline

Introduction
 Project structure




Technical status




Working Team
Communication
Composition of WP2
WP2-1
WP2-2 and 2-3
Resources
Conclusion
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Resources
Funds
To be spent
Foreseen
before 31/12 balance 31/12
Allocation
Spent
WP2-1 and 2-3
160 K
94 K
18 K
48 K
WP 2-2 CERN
15 K
15 K
-
-
WP 2-2 EU
65 K
3K
24K
38 K
Manpower
- Very good, young and motivated team. Experience acquired through consultancy
- Size adequate (addition of 1 fellow in mid-09)
- 1 staff LD crucial to ensure continuity of the project (main designer is MC fellow)
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Conclusion

Excellent progress in the first months of activity

Work started also on deliverables for 2011!

WP activity well on-budget
 Activity focused on DC-DC converters – following
demand from the experiments
 If appropriate continuity is ensured in terms of
manpower and funds, WP2 will provide a viable
solution for the SLHC experiments
PH Theme 3 meeting
November 11, 2008
CERN - PH dept – ESE group
43