Transcript EE4800 CMOS Digital IC Design & Analysis

EE4800 CMOS Digital IC Design & Analysis
Lecture 1 Introduction
Zhuo Feng
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
■ Prof. Zhuo Feng
► Office: EERC 513
► Phone: 487-3116
► Email: [email protected]
■ Class Website
► http://www.ece.mtu.edu/~zhuofeng/EE4800Fall2011.html
► Check the class website for lecture materials, assignments
and announcements
■ Schedule
► TR 12:35pm-13:50pm EERC 227
► Office hours: TR 4:30pm – 5:30pm or by appointments
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Topics (tentative)
■ Introduction
■ CMOS circuit and layout
■ MOS transistor device characteristics
■ DC and transient responses, delay estimation
■ Logical effort
■ Power
■ SPICE simulation
■ Modified Nodal Analysis (MNA)
■ Interconnect
■ Combinational circuits
■ Sequential circuits
■ Design for Testability
■ Adders
■ SRAM
■ Packaging, power and clock distributions
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Grading Policy
■ Homework: 40%
■ Quizzes 10%
■ Mid-term Exam: 20%
■ Final Exam: 30%
■ Late homework: 50% penalty/day.
■ Letter Grades:
► A: 85~100; AB: 80~84; B: 75~79; BC: 70~74; C:
65~69; D: 60~64; F: 0~59
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Moore’s law in Microprocessors
Transistors (MT)
1000
2X growth in 1.96 years!
100
10
486
1
0.1
0.01
P6
Pentium® proc
386
286
8086
8085
8080
8008
4004
0.001
1970
1980
1990
Year
2000
2010
Transistors on Lead Microprocessors double every 2 years
Courtesy, Intel
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Die Size Growth
Die size (mm)
100
10
8080
8086
8085
8008
4004
1
1970
1980
386
286
P6
Pentium
® proc
486
~7% growth per year
~2X growth in 10 years
1990
Year
2000
2010
Die size grows by 14% to satisfy Moore’s Law
Courtesy, Intel
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Frequency
Frequency (Mhz)
10000
Doubles every
2 years
1000
100
10
8085
1
0.1
1970
8086 286
386
486
P6
Pentium ® proc
8080
8008
4004
1980
1990
Year
2000
2010
Lead Microprocessors frequency doubles every 2 years
Courtesy, Intel
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Power Dissipation
100
Pentium ®proc
Power (Watts)
P6
10
8086 286
1
8008
4004
486
386
8085
8080
0.1
1971
1974
1978
1985
Year
1992
2000
Lead Microprocessors power continues to increase
Courtesy, Intel
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Why Scaling?
■ Technology shrinks by ~0.7 per generation
■ With every generation can integrate 2x more
functions on a chip; chip cost does not increase
significantly
■ Cost of a function decreases by 2x
■ But …
► How to design chips with more and more functions?
► Design engineering population does not double every two
years…
■ Hence, a need for more efficient design methods
► Exploit different levels of abstraction
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Pentium 4
Deep pipeline (2001)
► Very fast clock
► 256-1024 KB L2$
■ Characteristics
► 180 – 65 nm process
► 42-125M transistors
► 1.4-3.4 GHz
► Up to 160 W
► 32/64-bit word size
► 478-pin PGA
■ Units start to become
invisible on this scale
■
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Pentium M
Pentium III derivative
► Better power efficiency
► 1-2 MB L2$
■ Characteristics
► 130 – 90 nm process
► 140M transistors
► 0.9-2.3 GHz
► 6-25 W
► 32-bit word size
► 478-pin PGA
■ Cache dominates chip area
■
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Core2 Duo
Dual core (2006)
► 1-2 MB L2$ / core
■ Characteristics
► 65-45 nm process
► 291M transistors
► 1.6-3+ GHz
► 65 W
► 32/64 bit word size
► 775 pin LGA
■ Much better
performance/power
efficiency
■
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Core i7
■ Quad core (& more)
► Pentium-style architecture
► 2 MB L3$ / core
■ Characteristics
► 45-32 nm process
► 731M transistors
► 2.66-3.33+ GHz
► Up to 130 W
► 32/64 bit word size
► 1366-pin LGA
► Multithreading
■ On-die memory controller
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Atom
■ Low power CPU for netbooks
► Pentium-style architecture
► 512KB+ L2$
■ Characteristics
► 45-32 nm process
► 47M transistors
► 0.8-1.8+ GHz
► 1.4-13 W
► 32/64-bit word size
► 441-pin FCBGA
■ Low voltage (0.7 – 1.1 V) operation
► Excellent performance/power
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
D
n+
Design Metrics
■ How to evaluate performance of a digital
circuit (gate, block, …)?
► Cost
► Reliability
► Scalability
► Speed (delay, operating frequency)
► Power dissipation
► Energy to perform a function
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Cost of Integrated Circuits
■ NRE (non-recurrent engineering) costs
► design time and effort, mask generation
► one-time cost factor
■ Recurrent costs
► silicon processing, packaging, test
► proportional to volume
► proportional to chip area
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Cost per Transistor
cost:
¢-per-transistor
1
0.1
Fabrication capital cost per transistor (Moore’s law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982 1985
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1988 1991
1994
1997 2000
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
2003 2006
2009 2012
Silicon Lattice
■ Transistors are built on a silicon substrate
■ Silicon is a Group IV material
■ Forms crystal lattice with bonds to four neighbors
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Si
Si
Si
Si
Si
Si
Si
Si
Si
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Dopants
■ Silicon is a semiconductor
■ Pure silicon has no free carriers and conducts poorly
■ Adding dopants increases the conductivity
■ Group V: extra electron (n-type)
■ Group III: missing electron, called hole (p-type)
Si
Si
Si
Si
Si
Si
As
Si
Si
B
Si
Si
Si
Si
Si
-
+
N-type
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+
-
Si
Si
Si
P-type
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
P-N Junctions
■ A junction between p-type and n-type
semiconductor forms a diode.
■ Current flows only in one direction
Current flow direction
p-type
n-type
Electron flow direction
anode
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cathode
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
NMOS Transistor
■ Four terminals: gate, source, drain, body
■ Gate – oxide – body stack looks like a capacitor
► Gate and body are conductors
► SiO2 (oxide) is a very good insulator
► Called metal – oxide – semiconductor (MOS) capacitor
► Even though gate is no longer made of metal
Source
Gate
Drain
Polysilicon
SiO2
n+
Body
p
n+
bulk Si
Substrate, body or bulk
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
NMOS Operation
■ Body is commonly tied to ground (0 V)
■ When the gate is at a low voltage:
► P-type body is at low voltage
► Source-body and drain-body diodes are OFF
► No current flows, transistor is OFF
Source
Gate
Drain
Polysilicon
SiO2
0
n+
n+
S
p
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bulk Si
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
D
NMOS Operation Cont.
■ When the gate is at a high voltage:
► Positive charge on gate of MOS capacitor
► Negative charge attracted to body
► Inverts a channel under gate to n-type
► Now current can flow through n-type silicon from source
through channel to drain, transistor is ON
Source
Gate
Drain
Polysilicon
SiO2
1
n+
n+
S
p
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bulk Si
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
D
PMOS Transistor
■ Similar, but doping and voltages reversed
► Body tied to high voltage (VDD)
► Gate low: transistor ON
► Gate high: transistor OFF
► Bubble indicates inverted behavior
Source
Gate
Drain
Polysilicon
SiO2
p+
p+
n
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
bulk Si
Power Supply Voltage
■ GND = 0 V
■ In 1980’s, VDD = 5V
■ VDD has decreased in modern processes
► High VDD would damage modern tiny transistors
► Lower VDD saves power
■ VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Transistors as Switches
■ We can view MOS transistors as electrically
controlled switches
■ Voltage at gate controls path from source to
drain
d
nMOS
pMOS
g=1
d
d
OFF
g
ON
s
s
s
d
d
d
g
OFF
ON
s
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g=0
s
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
s
CMOS Inverter
A
VDD
Y
0
1
A
A
Y
Y
GND
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
CMOS Inverter
A
VDD
Y
0
1
OFF
0
A=1
Y=0
ON
A
Y
GND
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
CMOS Inverter
A
Y
0
1
1
0
VDD
ON
A=0
Y=1
OFF
A
Y
GND
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
CMOS NAND Gate
A
B
0
0
0
1
1
0
1
1
Y
Y
A
B
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
0
1
1
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ON
ON
Y=1
A=0
B=0
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
OFF
OFF
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
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OFF
ON
Y=1
A=0
B=1
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
OFF
ON
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
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ON
A=1
B=0
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
OFF
Y=1
ON
OFF
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
0
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OFF
A=1
B=1
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
OFF
Y=0
ON
ON
CMOS NOR Gate
A
B
Y
0
0
1
0
1
0
1
0
0
1
1
0
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A
B
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Y
3-input NAND Gate
■ Y pulls low if ALL inputs are 1
■ Y pulls high if ANY input is 0
Y
A
B
C
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
CMOS Fabrication
■ CMOS transistors are fabricated on silicon wafer
■ Lithography process similar to printing press
■ On each step, different materials are deposited or
etched
■ Easiest to understand by viewing both top and
cross-section of wafer in a simplified
manufacturing process
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Inverter Cross-section
■ Typically use P-type substrate for NMOS
transistors
■ Requires N-well for body of PMOS transistors
► Silicon dioxide (SiO2) prevents metal from shorting to other
layers
input A
GND
VDD
Y
SiO2
n+ diffusion
n+
n+
p+
p+
n well
p substrate
nMOS transistor
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p+ diffusion
polysilicon
metal1
pMOS transistor
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Well and Substrate Taps
■ P-type substrate (body) must be tied to GND
■ N-well is tied to VDD
■ Use heavily doped well and substrate contacts (
taps)
► Establish a good ohmic contact providing low resistance for
bidirectional current flow
A
GND
VDD
Y
p+
n+
n+
p+
p+
n well
p substrate
substrate tap
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
well
tap
n+
Inverter Mask Set
■ Transistors and wires are defined by masks
► Inverter can be obtained using six masks: n-well,
polysilicon, n+ diffusion, p+ diffusion, contacts and metal
■ Cross-section taken along dashed line
A
Y
GND
VDD
nMOS transistor
pMOS transistor
substrate tap
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
well tap
Detailed Mask Views
■ Six masks
► n-well
n well
► Polysilicon
Polysilicon
► N+ diffusion
n+ Diffusion
► P+ diffusion
► Contact
p+ Diffusion
Contact
► Metal
Metal
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Fabrication
■ Chips are built in huge factories called fabs
■ Contain clean rooms as large as football fields
Courtesy of International
Business Machines (IBM) Corporation.
Unauthorized use not permitted.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Fabrication Steps
■ Start with blank wafer
■ Build inverter from the bottom up
■ First step will be to form the n-well
► Cover wafer with protective layer of SiO2 (oxide)
► Remove layer where n-well should be built
► Implant or diffuse n dopants into exposed wafer
► Strip off SiO2
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Oxidation
■ Grow SiO2 on top of Si wafer
► 900 – 1200 Celcius with H2O or O2 in oxidation
furnace
SiO2
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Photoresist
■ Spin on photoresist
► Photoresist is a light-sensitive organic polymer
► Softens where exposed to light
Photoresist
SiO2
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Lithography
■ Expose photoresist through n-well mask
■ Strip off exposed photoresist
Photoresist
SiO2
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Etch
■ Etch oxide with hydrofluoric acid (HF)
■ Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Strip Photoresist
■ Strip off remaining photoresist
► Use mixture of acids called piranha etch
■ Necessary so resist doesn’t melt in next step
SiO2
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
N-well
■ N-well is formed with diffusion or ion implantation
■ Diffusion
► Place wafer in furnace with arsenic gas
► Heat until As atoms diffuse into exposed Si
■ Ion Implantation
► Blast wafer with beam of As ions
► Ions blocked by SiO2, only enter exposed Si
SiO2
n well
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Strip Oxide
■ Strip off the remaining oxide using HF
■ Back to bare wafer with n-well
■ Subsequent steps involve similar series of steps
n well
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Polysilicon
■ Deposit very thin layer of gate oxide (SiO2)
► < 20 Å (6-7 atomic layers)
■ Chemical Vapor Deposition (CVD) of silicon layer
► Place wafer in furnace with Silane gas (SiH4)
► Forms many small crystals called polysilicon
► Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Polysilicon Patterning
■ Use same lithography process to pattern
polysilicon
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Self-Aligned Process
■ Use oxide and masking to expose where n+
dopants should be diffused or implanted
■ N-diffusion forms NMOS source, drain, and nwell contact
n well
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
N-diffusion
■
■
■
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
n+ Diffusion
n well
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
N-diffusion cont.
■ Historically dopants were diffused
■ Usually ion implantation today
■ But regions are still called diffusion
n+
n+
n+
n well
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
N-diffusion cont.
■ Strip off oxide to complete patterning step
n+
n+
n+
n well
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
P-Diffusion
■ Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
p+
n+
n+
p+
p+
n well
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
n+
Contacts
■ Now we need to wire together the devices
■ Cover chip with thick field oxide
■ Etch oxide where contact cuts are needed
Contact
Thick field oxide
p+
n+
n+
p+
p+
n well
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
n+
Metallization
■ Sputter on aluminum over whole wafer
■ Pattern to remove excess metal, leaving wires
Metal
Metal
Thick field oxide
p+
n+
n+
p+
p+
n well
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
n+
Layout
■ Chips are specified with set of masks
■ Minimum dimensions of masks determine
transistor size (and hence speed, cost, and
power)
■ Feature size f = distance between source and
drain
► Set by minimum width of polysilicon
■ Feature size improves 30% every 3 years or so
■ Normalize for feature size when describing
design rules
■ Express rules in terms of l = f/2
► E.g. l = 0.3 mm in 0.6 mm process
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Simplified Design Rules
■ Conservative rules to get you started
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Inverter Layout
■ Transistor dimensions specified as Width / Length
► Minimum size is 4l / 2l, sometimes called 1 unit
► In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Summary
■ MOS Transistors are stack of gate, oxide, silicon
■ Can be viewed as electrically controlled switches
■ Build logic gates out of switches
■ Draw masks to specify layout of transistors
■ Now you know everything necessary to start
designing schematics and layout for a simple chip!
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis