Transcript Summary of Workshop (260601) on ALICE Detector LV Power G

ALICE Silicon Pixel Detector (SPD)
G. Stefanini/CERN-EP
 General
 Front-end electronics
– pixel bus
– ALICE1 ASIC
– PILOT ASIC, bias ASIC, optical link package, MCM
 Silicon sensors
 Beam test with bump-bonded assemblies
 Pixel wafer probing
 Pixel wafer thinning
 Mechanics and cooling
 Summary - Planning
16/11/01
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SPD (Hybrid Pixels) - Design Parameters
 Two barrel layers
Ri= 39mm, Ro = 76mm
 Pixel cell dimensions
50mm (r f) x 425mm (z)
 Front-end electronics
CMOS6 0.25mm standard process on 8” wafers,
rad-hard design
 Pixel ASIC thickness (target)
≤ 150mm (wafers thinned after bump deposition)
 Si sensor ladder thickness
≤ 200mm
 Flip-chip
solder bumps/indium bumps
 Pixel bus
aluminium-polyimide flex
 Cooling
water/C6F14/[C3F8 (evaporative)]
 Material budget (each layer)
≈ 0.9% X0 (Si ≈ 0.37, cooling ≈ 0.3, bus 0.17, support ≈ 0.1)
 Total Si surface
≈ 0.24 m2
 Occupancy
< 2%
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SPD Mechanical Configuration (I)
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SPD Mechanical Configuration (II)
2 barrel layers
z= ± 14.15cm (sensitive)
r1 = 3.9 cm, r2 = 7.6 cm
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SPD Ladders & Staves
1 sector
one carbon-fibre support for layer 1+2
readout of 120 half-staves in parallel
4 staves in outer layer
2 staves in inner layer
ladder (1 sensor, 5 chips)
half-stave: 2 ladders
SPD total 1200 pixel chips, ≈ 107 pixels
Image: INFN Padova
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Pixel Bus & Ladders (I)
± 193 mm
ladder2
ladder1
Power supplies connector
Extenders (Copper-capton)
Flexible Extender
70.72 mm
70.72 mm
MCM
1000mm
 Pixel bus: multilayer flex Al-polyimide
 So far, only satisfactory technology source is the EST PCB Workshop
 A-prototype (Cu) under test for signal integrity with 10 chips on bus
 B-prototype (Al) layout to start in Jan 02 (workload in EST layout section)
 Explore feasibility with industrial company
M. Morel
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Pixel Bus & Ladders (II)
11mm
SMD component
7
7
7
6
7
6
5
5
4
235µm
PIXEL_BUS
3
2
2
1
Aluminium
1
Polyimide
Glue
PIXEL DETECTOR
<350µm (design target)
READOUT CHIP
?
CARBON FIBER SUPPORT
COOLING TUBE
1 ANALOG_GND 25µ
2 ANALOG_ POWER 25µ
3 HORIZONTAL LINES 10µ
4 VERTICAL LINES 5µ
5 DIGITAL_POWER 25µ
6 DIGITAL_GND 25µ
7 RES + CAPA PADS 15µ
M. Morel
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End Stave Connections (I)
Connections details of pixel_carrier and extenders
Bias 2
BIAS 2 (10uA)
BIAS 1 (10uA)
Bias 1
AGND
AGND
VTT (1A)
Sense (VTT)
SENSE
GND (VTT)
VTTA (0.1A)
Sense (VTTA)
AGND (VTTA)
VDDA
MCM_Dig (1A)
Sense (MC M_Dig)
RESISTOR TO
VTT
VDD
DECOUPLING
CAPACITOR
GND
GND (MCM _DIG)
MCM_A (?)
SENSE
Sense
BIAS
DECOUPLING
CAPACITOR
VDD
AGND
AGND
VDDA
SIG
VDD
GND
Pixel chip
Pixel de tector
Pilot MCM
Note: the drawing is not to scale
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Al pixel carri er
Cu extender 1
1
Cu extender 2
Michel Morel EP/ED 09/2001
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ALICE Pixel ASIC
• CMOS6 0.25 µm (8” wafers)
• Radiation hard design (enclosed transistors)
• ≈ 13.106 transistors
• 8192 pixel cells 50 µm x 425 µm
• 256 rows, 32 columns
• Active area: 12.8mm x 13.6mm
• 10 MHz clock
• 1.8V power supply
• ~100 µW/channel
M. Campbell
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Pixel Cell
M. Campbell
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Pixel Chip JTAG Controls
 All configuration parameters are controlled through JTAG bus
 Two-fiber optical link, effective clock frequency 5 MHz
 Global registers
– 42 DACs for biasing
– strobe delay
– global threshold voltage
– miscellaneous control (leakage current compensation, delay unit)
 Local registers (for each pixel cell):
– 3 bit threshold adjustment
– TEST Enable
– Pixel mask
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Test Set-Up
•DAQ
LabView
•Analysis ROOT
•Database MySQL
VME
Master
JTAG
Controller
R/O
Controller
Pixel
Chip
Pixel Chip
Carrier
DAQ
Adapter
P. Chochula
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Radiation Test - Single Event Upsets (SEU)
Hadrons may interact elastically and inelastically with Si atoms
 recoils and fragments deposit a large amount of charge in the chip
 Single Event Effect
SEGR (Gate Rupture)  breakdown of transistor gate
SEL (Latch-up)  high power supply current
SEU (Upset)  switch logical level
Mitigation: all critical memory cells are hardened by built-in redundancy
Alice1LHCb:
8192 Pixels:
42 DACs:
5 memory cells each (3 threshold adjust, 1 mask, 1 test)
8 memory cells each (8 bit DACs)
J. Van Hunen
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SEU Cross Section (I)
SEU Cross Section (cm 2)
Measure SEU cross-section as function of the Linear Energy
Transfer (LET) - at Louvain cyclotron (ions and protons)
1.E-06
1.E-07
1.E-08
chip 43
1.E-09
chip 72
1.E-10
Weibull
1.E-11
0
20
40
60
80
100
120
LET (MeV mg-1cm2)
The LET is measured first with heavy ions Xe26+, Kr17+, etc., under
different angles of incidence to cover the required range.
J. Van Hunen
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SEU Cross Section (II)
The heavy ion results are used to calculate the SEU cross section for
exposure to protons (60 MeV) :  9 10-16 cm2 per memory cell
Measurement with 60 MeV protons:
Fluence
(cm-2)
# SEUs
# irradiated cells
Cross Section
(cm2)
6.4 1012
84
41,296
3 10-16
For the ALICE pixel detector:
1200 chips, 336 DAC bits  0.1 bit/hour
J. Van Hunen
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Pixel Chip Testing
Four identical test setups have been installed in the CERN lab.
• Test of all internal DACs
• Threshold and noise scans
• Minimum threshold
• Current consumption
• Tests of the individual stages
• Functionality of the JTAG
•Used also for SEU measurements
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Bare Chip Threshold Scan
Pulse each row (e.g. 250
triggers) with test-pulse (e.g. 050 mV).
Mean threshold: ~14-15mV
RMS ~3mV.
No individual threshold adjust.
Conversion factor: ~66e-/mV
(preliminary!)
~1000 e- mean threshold
~ 200 e- RMS
P. Riedler
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Bare Chip Threshold Scan (II)
Mean threshold vs. global threshold setting
3811
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2111
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Electrons RMS
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Bare Chip Noise Scan
Determined from S-curve.
Mean noise ~1.7-2 mV
RMS ~ 0.2 mV
Mean noise ~110 e- RMS
P. Riedler
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Test Pulse
Threshold map
• measured on chip 52
• scale in mV
• pulser located under column 5
P. Riedler
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Fast Multiplicity for Trigger
 Fast Multiplicity: prompt analog output from each chip
 Half-stave sum ==> multiplicity in left and right part of barrel (Ml, Mr)
 Ml+Mr ==> total on SPD barrel ==> trigger on centrality
 Ml-Mr ==> left-right asymmetry ==> trigger on position of primary vertex (s ≈ few mm)
 Implementation study under way
– analog optical signal transmission
– contribution to L0 ? ( <1ms latency)
 Constraints on performance at very low multiplicity
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Engineering & Pre-production Wafers
 All tests so far with 6 engineering run wafers
 Some imperfections in design, but performance of the chip “as is” meets essential
specs. Use of ladder Fast-OR and very low Fast Multiplicity would require partial
redesign. Final decision in Q2/02.
 Exceptional new lot of 48 wafers just delivered
– ALICE
– NA60
– LHCb, ..
≈ 24
16
≈ 8
 New ALICE lot: optimisation of bump-bonding and wafer thinning
– allows some flexibility in deadline for decision on final production
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pixel
chip 9
Half-Stave Readout Electronics Chain
G-link
pixel
chip 0
pixel
pilot
pixel chips
pixelbus
pixel transmit opt.
link
serializer&
optics
busy, jtag
pixelcontro l
receive
pilot MCM
link
receiver
pixel
converter
pixel
router
opt.
links
pixelco nt rol
transmit
L1, L2y, L2n,
testpulse, jtag
control room
A. KLuge 25.1.01
A. Kluge
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PILOT ASIC
• CMOS6 0.25mm
• Rad-hard design
• Dimensions 4mm x 6mm
• JTAG controls
• clock recovery and distribution
• half-stave data out
• level conversion
• multiplexing
• interface to Gigabit Optical Link (GOL)
• (serialiser/driver ASIC)
• currently under test (Nov 01)
A. Kluge
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Bias ASIC - Optical link package
 Bias ASIC : generates reference levels for the pixel chip
– design (≈ 3 months) to start in Jan 02 (EP-MIC)
– submission in MPW
– might be on critical path for MCM
 Optical link package (1 laser diode, 2 PIN diodes, overall thickness < 1.4mm)
– development under way
– functional prototype ≈ end March 02
– full production will take ≈ 3 months
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Silicon Sensors
 p+ on n with guard rings, each wafer (5”) has 5 ladders + 13 singles
 Prototypes
– 300mm thickness
15 wafers
– 200mm thickness
3 wafers
available
available (+ 2 in order)
 CERN Market Survey MS-3087/EP/ALICE sent out to firms on 12 Nov 01
 Closing date: 21 Dec 01
 Examination of replies: Jan 02 (2nd week)
 Invitation to tender will be issued by INFN (Catania/Roma 1)
– Committee already appointed
– deadline: within Q1/02
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Bump-bonding - Assemblies
Detector
Chip
First delivered ≈ 10 assemblies:
Sensors: p+ on n, thickness 300µm
Chips: Lot 1 (750µm thick) - unprobed wafers!
Assemblies produced by:
AMS/Italy
Indium bumps
stand-off ~ 10µm
VTT/Finland
Pb-Sn solder bumps
stand-off ~15µm
P. Riedler
16/11/01
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Assemblies - Threshold Scan
Threshold measurement:
VTT 8
Mean threshold: 21.2 mV
RMS: 2.8 mV
Similar to measurement on
bare chip.
P. Riedler
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Assemblies - Noise Scan
Noise measurement:
VTT 8
Mean noise: 1.97 mV
RMS: 0.24 mV
Similar to noise on bare chip.
P. Riedler
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Threshold Scan on Assemblies
50mV ≈ 3,200 eP. Riedler
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Assemblies - Source Tests
Source tests were carried out on all assemblies, using:
Source
Electrons RMS
Sr 90
Cd 109
Fe 55
2.28 MeV electrons
~22+25 keV gammas (electrons shielded)
~6keV gammas
~63 300
~6100
~1600
• Bump-bonding quality
• Calibration
• Threshold adjustment
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Assemblies - Sr90 Source
Bump-bonding quality
Assembly VTT 10
Bias: 80V
Sr-source
P. Riedler
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Assemblies - Fe55 Source
No threshold adjust
With threshold adjust
glue drop
P. Riedler
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Beam Test with Assemblies
13-25 July (Period 1) and 1-9 September, 2001 (Period 2)
H4 beam-line in the NA57 area
• 150 GeV/c pions
• 105-106 particles/spill
• ~10 x 5 mm2 beam-focus
• Scintillator trigger selects 2 x 2 mm2 beam-spot
Period 1: one plane, 2 assemblies tested
Period 2: telescope (3 planes), 5 assemblies tested
analysis under way
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Beam Test Set-Up (I)
C1A
Assembly 0
scintillator S3
beam
C2
~10m
C1B
Assembly 1
Assembly 2
x-y table
two small scintillators
orthogonal to each other
MB
card
MB
card
power supply
power supply
MB
card
power supply
Full telescope (for Period 1 only the centre assembly was mounted)
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Beam Test Set-Up (II)
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Beam Profile
VTT 12
Beam profile in z (425 µm pixels): ~ 7 pixels = 3 mm
Beam profile in x ( 50 µm pixels): ~50 pixels = 2.5 mm
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Bias Scan
Sensor thickness 300mm
100
Online Efficiency [%]
80
60
40
VTT 1
th=215 ~ 1600 electrons RMS
th=200 ~ 2900 electrons RMS
20
0
0
20
40
60
80
Bias Voltage [V]
Normalization to scintillating counters - preliminary!
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Cluster Size Analysis
(preliminary, from run with 1 assembly)
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First ALICE Pixel Ladder from VTT
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Pixel Wafer Probing (I)
Each wafer contains 86 ALICE1LHCb chips.
Tests carried out on each chip:
• Current consumption (analogue/digital)
• JTAG functionality
• Scan of all DACs
• Determination of minimum threshold
• Complete threshold scan of pixel matrix
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Pixel Wafer Probing (II)
Class I
Class II
Fully functional, but
less than 6000 pixels
responding to the
threshold scan
Class III
Masking problems, high
or asymmetric noise or
threshold
Class IV
Excessive or no current
No response from the chip
P. Riedler
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Pixel wafer thinning
 Pixel wafers will be thinned after bump deposition (processed side protected)
 VTT has equipment and expertise in this field
 Preliminary trials with 4” and 8” blank wafers with SPD bump pattern
– wafers thinned down to <100mm
– backside free from bump imprint
 Imminent trial with real probed pixel wafers
– check if thinning affects performance
– determine practical limit
 Bump-bonding thinned chips and ladders is next major challenge
– development program under way
– completion expected in June 02
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Mechanics & Cooling
Items to be produced:
Carbon fiber support structure: 10 sectors (turbo_like disposition)
Two halves cylinder-cone support structure working also as thermal screen towards SDD and air
flow channelling
Tooling for stave assembly, detector assembly etc.
TEST already done:
Prototypes of CFSS made out of different CF tape thickness and resin (epoxy, cyanate ester). The
final geometry is not yet assessed (sector length, cooling system choice, etc.).
The main efforts are on integration scenario definition and cooling system design & test.
A. Pepato
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SPD Sector (II)
A. Pepato
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Cooling Test Bench
A
B
A
50 mm kapton
25 mm copper
60 mm epoxy resin
125 mm kapton
50 mm cond. grease
40 mm SS cooling
B
1 mm FR4
25 mm copper
50 mm cond. grease
40 mm SS cooling
A. Pepato
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Summary - Planning
 Pixel ASIC meets essential specs. KGD yield from engineering wafers ≈ 35%
 Pre-production wafer lot procured
 Sensors market survey sent out
 Bump-bonding optimisation and wafer thinning trials in progress
 FE electronics chain under test
 Pixel bus prototyping nearly completed
 Key electronic issues under study: signal integrity on bus, end-stave connections,
grounding, power distribution (rad-hard voltage regulators in patch-panels), etc
 Mechanics & cooling well defined, corrosion study under way ==> choice of coolant
 Completion of all developments by Q3/02, production to start in Q4/02
 Detailed planning reviewed Nov 01
 Challenge ahead: detector assembly and integration (ladders, bus, glueing, wire bonding,
mounting on sectors, final tests)
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