Transcript Pixel Hybride 3-D en techno 0.13µm pour SLHC/ATLAS

Pixel Hybride 3-D en techno
0.13µm pour SLHC/ATLAS
S. Godiot a, M. Barbero b, B. Chantepie a, J.C. Clémens a, R. Fei a, J. Fleury c, D.
Fougeron a, M. Garcia-Sciveres c, T. Hemperek b, M. Karagounis b, H. Krueger b, A.
Mekkaoui c, P. Pangaud a, A. Rozanov a, N. Wermes b
a
Centre de Physique des Particules de Marseille, France
b University of Bonn, Germany
c Lawrence Berkeley National Laboratory, California, USA
Ecole micro-électronique, La londe-les-maures, 14 oct 2009
Outline
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Pixel pour Atlas/LHC
Projet SLHC
Version 3D
MPW TERRAZON/CHARTERED
Ecole micro-électronique, La londe-les-maures, 14 oct 2009
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Pixels pour upgrade de Atlas/LHC
Constraints
4
bits
5
bits
Config
word=1
2b
Noise under 100eThreshold around 1000eDispersion threshold 200e-
CF=17fF CC/CF2=5.8
Ecole micro-électronique, La londe-les-maures, 14 oct 2009
P.Pangaud
FE-I4/FE-TC4 : Analog Preamplifier
Leakage Comp. Transistor
Local Feedback tuning 4b
Feedback structure
Injection switches
and caps
Core Preamp
Ecole micro-électronique, La londe-les-maures, 14 oct 2009
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50 μm
Hybrid Pixels detector for HEP
(Atlas/LHC example)
FE-I3 CMOS
technology : 250 nm
50 μm
400 μm
Done : ATLAS/LHC
(2008/2009)
FE-I4 CMOS
technology : 130 nm
250 μm
Under Design
ATLAS/LHC upgrade
project
(2014…)
And silicon sensor with the same pixel dimension
Ecole micro-électronique, La londe-les-maures, 14 oct 2009
P.Pangaud
50 μm
3-D Hybrid Pixels detector
(Atlas/SLHC example)
FE-I3 CMOS
technology : 250 nm
Done : ATLAS/LHC
2008/2009
50 μm
400 μm
FE-I4 CMOS
technology : 130 nm
50 μm
250 μm
50 μm
125 μm
100 μm
Under Design
ATLAS/LHC
upgrade project
(2014…)
Drastic pixel dimension
reduction (cost effective
compared to smallest
technologies ?)
New
mechanical
possibilities
Ecole micro-électronique, La londe-les-maures, 14 oct 2009
Why not ??
ATLAS/SLHC
(10 years after LHC..)
Dream,dream,dream ???
ATLAS/SLHC
P.Pangaud
Pixel -> 3-D
4
bits
5
bits
Config
word=1
2b
FE-TC4-EA :
2 possible ways for
discriminator output
read-out:
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With the simple read-out
part existing yet into the
pixel
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With the tier 2 (via the
Bond Interface)
FE-TC4-DS :
dedicated for
parasitic coupling studies
between the 2 tiers.
FE-TC4-DC :
CF=17fF CC/CF2=5.8
Ecole micro-électronique, La londe-les-maures, 14 oct 2009
Read-out chip similar to what
is foreseen for FE-I4
P.Pangaud
FE-I4 to FE-TC4
FEI4 : IBM 0.13µ
1P8M LV
FEI4 : CHARTERED 0.13µ
1P5M LP
• Bond Interface
5µm step
• TSV
1.5µ diameter
Ecole micro-électronique, La londe-les-maures, 14 oct 2009
P.Pangaud
->
:
Counter + parasitic coupling studies
Complex : Read-out chip similar to what is foreseen for FE-I4
Back Side Metal
SuperContact
M1
M2
M3
M4
M5
M6
M6
M5
M4
M3
M2
M1
Tier 1
(thinned wafer)
sensor
-> Simple
10µm
Bond Interface
5µm
Tier 2
2d Tiers
SuperContact
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P.Pangaud
Fermilab 3-D Multi-Project Run
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Fermilab has planned a dedicated 3-D multi project run using Tezzaron for
HEP during 2009
There are 2 layers of electronics fabricated in the Chartered 0.13 um
process, using only one set of masks. (Useful reticule size 15.5 x 26 mm)
The wafers are bonded face to face.
ATLAS/SLHC
Sub-part
Ecole micro-électronique, La londe-les-maures, 14 oct 2009
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Fermilab 3-D Multi-Project Run
The Atlas/SLHC prototype
with 2 tiers
SEU-3D
SEU-3D
FETC4-AE
SENSOR
FETC4-DSDC
TSV Daisy Chain + BI
TSV vs Transistors
Mechanical stress
DFF + Tr + Cap
Ecole micro-électronique, La londe-les-maures, 14 oct 2009
TSV vs Transistors
+ capacitors
P.Pangaud
FEC4 -> First results of first chip in
Chartered 0.13LP 1P8M
• Due to schedule no optimization of transistors
has been done
Thin (mV)
• Main results are equivalent to IBM ones.
Threshold min around 1100 eUn-tuned threshold dispersion
200 eNoise lower than 80 e-
Problem discovered after 160
MRad on latches ( output tends to
be blocked in "1" state)
Difficult to work with the
circuit by
after
Problem reproduced in
simulation
"corners" (SF and FS case)
… but
Analog is still working
even with
Vthin
vs Dac value
increased of noise : 250 e2000
(threshold
Irradiate
1000
dispersion is meaningless)
d
0
0
200 400
C4 (ref)
Thin dac value
Ecole micro-électronique, La londe-les-maures, 14 oct 2009
P.Pangaud