Transcript Lecture 29

Lecture #29 CMOS fabrication, clocked
and latched circuits
• Last lecture:
PMOS
– Physical structure
– CMOS
– Dynamic circuits (Ring oscillators)
• This lecture:
– CMOS fabrication
– Clocked and latched circuits
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CMOS PARAMETERS
3 generations of CMOS
Parameter
L (m)
IDS’ (A/[V-m])
V-1
VT V)
VDSAT V)
dOX nm)
CGS ‘fF/m2)
VDD V)
NMOS
(0.25m)
0.25
350
0.05
0.5
1
5
7
2.5
PMOS
(0.25m)
0.25
-175
0.05
- 0.5
-1
5
7
2.5
NMOS
(0.18m)
0.18
500
0.07
0.4
0.75
3.5
10
1.8
PMOS
(0.18m)
0.18
- 250
0.07
- 0.4
- 0.75
3.5
10
1.8
NMOS
(0.13m)
0.13
650
0.1
0.4
0.6
2.5
14
1.5
PMOS
(0.13m)
0.13
- 325
0.1
- 0.4
- 0.6
2.5
14
1.5
Return
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Interconnect layers
• On top of the transistor layers, many metal
layers interconnect the logic
Illustration
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Actual TEM photo
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MOS Fabrication and LAYOUT
Drain
contact
W
Gate (over oxide)
Source
contact
Device dimensions are
larger than gate
dimensions
Gate Length = L
L
Gate Width = W
Thick oxide
on silicon
Thin
oxide
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Integrated Circuit Fabrication
Goal: Mass fabrication (i.e. simultaneous fabrication) of hundreds of “Chips”,
each a circuit (such as a microprocessor or memory chip) containing millions
of transistors
Method: Lay down thin films of semiconductors, metals and insulators and
pattern each layer with a process much like printing (lithography).
Minimum set of materials in an integrated circuit
•
Si substrate
•
SiO2 insulator
•
Polysilicon gate
•
Metal contacts and wiring
Other materials generally used (but not discussed here)
Tungsten metal, Silicon nitride insulator, TiN and TiSi conductor regions
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Patterning the Layers - Lithography
Goal: Transfer the desired pattern information to the wafer
(for example the geometry of a wire)
Scheme: Subtractive Patterning … that means for example deposit
a uniform film of Aluminum and then selectively remove it (etch
it away) where you don’t want it.
Process for applying the pattern: Photolithography
How Photolithography works:
– Coat the the uniform film to be etched with a photosensitive
material
– Expose the photosensitive material with a “picture” of the desired
pattern (much like photographic printing)
– Develop away the exposed areas
– Use the resulting pattern to mask the etching of the underlying film
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Exposure Process
A glass mask with a black/clear pattern is used to expose a wafer
coated with about 1 m of photoresist (image projected with
optical system)
We will shine UV
light onto mask
Mask
Image of mask
will appear here
Lens
photoresist
oxide
Si wafer
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Review Exposure Process
• A glass mask with a black/clear pattern is used to expose a
wafer coated with about 1 m of photoresist
UV light
Mask
Image of mask
will appear here
(3 dark areas, 4
light areas)
Lens
photoresist
oxide
wafer
Areas exposed to UV light are susceptible to being chemically removed
(developed)
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Photoresist Development and Etching
•
Solutions with high pH dissolve the areas exposed to UV; unexposed
areas (under the black patterns) are not dissolved
Exposed areas of photoresist
oxide layer
After developing
the photoresist
Developed photoresist
oxide layer
After etching
the oxide
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oxide
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2004 layer
lecture 29
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CMOS
D
G
S
G
D
S
oxide
p
p
n-well
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n
n
P-Si
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Basic CMOS Inverter
Inverter
CMOS
Inverter
IN
VDD
OUT
IN
VDD
p-ch
OUT
n-ch
Al “wires”
IN
VDD
PMOS Gate
Example layout of
CMOS Inverter
N-WELL
OUT
NMOS Gate
GROUND
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Al “wires”
IN
VDD
PMOS Gate
N-WELL
OUT
NMOS Gate
GROUND
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Data Synchronization problem
• Combinatorial logic gates can give
incorrect answers prematurely and may
take several gate propagation delays
produce an answer.
• Clocks (signals as to when to proceed)
and latches (which capture and hold the
correct outputs) can provide
synchronization.
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Combinatorial vs Sequential logic
• In the digital circuits we have created so
far, the output was a function only of the
instantaneous inputs.
– combinational logic circuits.
• If the action of circuits depends on the
history of the inputs, or on past operations,
they are
– sequential logic circuits.
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Combinatorial
• A combinatorial circuit can be
schematically represented as a black box,
and is completely described by a truth
table of the outputs as a function of the
current inputs
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dynamic circuit
• the output is a function not only of the current inputs, but
of the internal state of the circuits, residual from previous
inputs. The circuit can not be described by a truth table
of the inputs only.
A
B
C
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Outputs
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Ring oscillator as an example of a dynamic circuit
VDD
STAGE 1
STAGE 101
Vout
At at time equal to exactly 1001 gate delays, the input to stage
1 will go high, and after another equal time it will go low, etc.
This is a “RING OSCILLATOR”, which toggles at a frequency
equal to 1/(1001 tdelay ).
Such ring oscillators are commonly used to estimate the
performance of a technology. No switch is actually needed, the
output is permanently wired to the input, and the oscillations
start when power is applied.
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Unpredictability of dynamic circuits
• In the case of the ring oscillator, the output
just oscillates forever without regard to its
inputs.
• If there are many different paths and
possible delays, the output of the circuit
can be highly unpredictable or chaotic,
because just what may happen at an
instant in time can depend on the exact
value of all the previous delays.
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Representing a Discrete Sequence
in Continuous Time
• From our viewpoint, time appears to be a
continuous variable.
• For a digital sequence, we want discrete values
• [x0,!x1, x2, x3, …], not a continuous function
x(t).
• The typical way to handle this is to use a clock.
• The continuous sequence is “sampled” at
regularly spaced times, when the clock “ticks”.
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Making time discrete
• The most common answer to this
complexity is the same one we used for
simplifying circuits before, but this now we
make time discrete.
• Rather than letting all of the internal nodes
take logical states at arbitrary times, we
use latches to prevent the change of state
of some nodes until a specific time.
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sequential circuit
• In a sequential circuit, the circuit can be
described by a truth table as a function of the
inputs and the values held byf internal latches.
A
B
C
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Outputs
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Dynamic Latch
VDD
To synchronize the data, L
remains low until the data is
correct. When L goes high the
inverse of the data is passed.
L
VOUT
VIN
COUT
L
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Note that in a dynamic latch,
the old value is just held by the
capacitance, which works in
CMOS because of the low
leakage of the switches, and the
fact that the next gate consumes
no current. When L is low, the
voltage at the output is left
floating
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Latches
• A latch remembers one bit, either a 0 or 1.
• The bit is held while the latch is low, until
the next time the latch is high.
• Each time the latch line pulses, whatever
value (0 or 1) exists at the flip-flop’s input
is remembered; the old value is lost.
• While the latch is high, the output will
follow the input
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Feedback Can Provide Memory
Feed back between gates can form a
circuit with static memory. This kind of
circuit is called a flip-flop
H
H
Q L
L
Q
H
H
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the Opposite State
H
L
Q H
H
H
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Q L
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Set/Reset
S
Q
Q
R
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Set/Reset flip-flop
• This circuit will do the following
1. If S=0 and R=0, Q will not change, but
will remember its former value.
2. If S=1 and R=0, then Q=1
3. If S=0 and R=1, then Q=0
4. S=1 and R=1 is an illegal combination
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Set/Reset flip-flop with clock
S
Q
φ
Q
R
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sequential circuit
• In a dynamic circuit with latches, we still
have a race when a latch passes a value,
of its output feeds back to its input.
A
B
C
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Outputs
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Two phase latches
• If we put two latches into every feedback path,
and make sure both latches are never open at
the same time, we can insure predicable results.
A
B
C
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Outputs
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Asynchronous vs. clocked logic
• One straightforward way of making sure that the
behavior is predictable, and does exactly what it
was designed to do, is to latch all of the circuits
in the block by one signal, which is called a
clock.
• If a dynamic circuit is built without a clock, it is
called asynchronous logic.
• It is possible to build fast, low power
asynchronous circuits, but difficult to make
complex systems which behave correctly
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Clocked logic
• If we put two latches into every feedback path,
and make sure both latches are never open at
the same time, we can insure predicable results.
A
B
C
Outputs

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