Transcript ginsburg_ogunnika

Adjustable Linear Range Operational Transconductance
Amplifier with Noise Compensation
Brian Ginsburg, Muyiwa Ogunnika
• Overall topology
– Basic WLR with bulk drive, gate degeneration, source degeneration
– Variable gain amplifier between drain and gate of the source
degeneration transistor to lower source degeneration
– Gate of input transistor driven with a weighted sum of its drain (for gate
degeneration) and the input voltage
– Current steering sets the VL and is compensated to keep noise low
• Theoretical linear range:
– Actual linear range varies
from 73mV to 1.25 V
2t  VL  2t
1 
1 
1

p
n
• N varies from 5.5 to 13.7
Ginsburg/Ogunnika 6.376 Final Presentation
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Block Diagram
gs
-A/gmp
+
Vin
gmb
+
+
vng
vns
2
iout
gm
1-A
gmp
1/gmn
A
2

p
n
VL  2t
1    (1  A)
1
A
A
0<A<1
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Variable Linear Range Performance
AwrlaTest
0.6
i(vout)
0.5
0.4
0.3
0.2
Current (uA)
• Linear range varies
from 73mV to 1.248V
• Each OTA has 45
transistors
• Common mode input
range is from 1.25V to
3 V at highest current
levels; increases to
0.85V-3V at low bias
current levels
• In resonant filter, f90
can vary from 100Hz
to 10kHz, and Q can
be variable from 1 to
6, though not for all VL
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
pvin ()
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Stability of the OTA
No load capacitor
1kHz bandwidth
100mV linear range
Unity-gain feedback
<5% overshoot in step
response
• OTA also stable with 10%
component mismatch
• Power with 5pF cap and
10kHz bandwidth <3.47μW
agmCFilter
v(vin)
v(vout)
2.10
2.05
2.00
Voltage (V)
•
•
•
•
•
1.95
1.90
1.85
1.80
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (ms)
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Circuit Details
I BS  I LVL  I HVL
Variable Gain Amplifier
I HVL
I LVL
A
 1
I BS
I BS
M=pmsd
M=pmsd
I=5uA
I=5uA
W='12*l'
L='6*l'
ILVLks
W='12*l'
L='6*l'
Vop
ILVLks
I=5uA
I=5uA
vtailvld
M=3
Bn
Von
M=2
Vin
IHVLkg
W='12*l'
L='6*l'
ILVLkg
vtailvli
M=3
W='12*l'
L='6*l'
An
Vcmb
W='12*l'
L='6*l'
Bp
M=2
Vcmb
Gate Drive Weighted Adder
M=3
M=3
W='12*l'
L='6*l'
W='12*l'
L='6*l'
Sn
M=2
W='12*l'
W='12*l'
L='6*l'
L='6*l'
Ap
Vip
Sp
M=2
M=2
W='12*l'
L='3*l'
W='12*l'
L='3*l'
vtailsd
2IBSks
I=5uA
Gain VGA 
n 1

p A
Ginsburg/Ogunnika 6.376 Final Presentation
p
VInGate   AVGD  (1  A)VIN 
n
5
Noise Impact of VL Variation
Effective number of
noise sources from
gate drive circuit:
•
Observations




4I B 


NG 
I BS k g    A  n  A 
 n


p


2
Theoretical N vs. VL
Dashed: Fixed kb
Solid: Variable kb
– For fixed VL, as IB drops, noise improves for fixed
IBS
– As VL decreases, noise shoots up
•
Solutions
–
–
–
–
•
•
For fixed VL, have IBS=kbIB
Make kb inversely dependent on VL
IBS=(1+6(1-A))IB/20
Power overhead varies from 30% to 130%
Actual N vs. VL
At Q=2, 10kHz
– VL=1.25, N=5.4
– 21.3μW
0.4dB variation from unity in passband, >50dB
attenuation at high frequencies
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Final Layout
• Fits in less than one
quarter of the chip!
• Most of the additional
circuitry is kept very
small
• Conclusions
• Questions
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