Transcript ARS-2003 Invited Talk - UCSD VLSI CAD Laboratory

On Design-Manufacturing Integration
Talk at Intel
June 25, 2003
Andrew B. Kahng, UCSD CSE & ECE Departments
email: [email protected]
URL: http://vlsicad.ucsd.edu
Andrew Kahng – June 2003
1
Outline
• The Problem, Scope and Goals
• Example: Cost-Driven RET
• Example: Intelligent MDP
• Example: Analog Rules, Restricted Layout, …
• Conclusions
Andrew Kahng – June 2003
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The Problem
• Steadily increasing design effort, turnaround time,
and project risk
• Example symptoms (next slides): detailed routing
• “Dark Future” (12th Japan DA Show talk, 2000)
– Cost and predictability failures 
– Electronics industry makes workarounds
• platforms  programmability  software 
– Semiconductor industry stalls 
– No retooling cycle for supplier industries (e.g., EDA)
• Cf. Intel announcement re 157nm lithography
Andrew Kahng – June 2003
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Reticle Enhancement (vs. Routing)
• 193nm, 157nm are late  , radius of influence >> F
• Pattern context increasingly dominant
– Iso vs. dense, microloading/halation, …
• RETs = knobs: aperture, phase, light, context
– Affect feasibility of mask write, verification
•  Complexity trend: model-based RETs, AIM tools in
the loop, test structure-based RLCX calibration, etc.
Andrew Kahng – June 2003
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Routing Rules (1)
• Minimum area rules and via stacking
– Stacking vias through multiple layers can cause minimum area
violations (alignment tolerances, etc.)
– Via cells can be created that have more metal than minimum
via overlap (used for intermediate layers in stacked vias)
• Multiple-cut vias
– Use multiple-cut vias cells to increase yield and reliability
• Can be required for wires of certain widths
– Multiple via cut patterns have different spacing rules
• Four cuts in quadrilateral; five cuts in cross; six cuts in 2x3 array; …
• With wide-wire spacing rules, complicates pin access
– Cut-to-cut spacing rules  check both cut-to-cut and metal-tometal when considering via-to-via spacing
• Line-end extensions
– Vias or line ends need additional metal overlap (0th-order OPC)
Andrew Kahng – June 2003
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Routing Rules (2)
• Width- and Length-dependent spacing rules
– Width-dependent rules: domino effects
– Variant: “parallel-run rule” (longer parallel runs  more
spacing)
– Measuring length and width: halo rules affect computation
• Influence rules or stub rules
– A fat wire, e.g., power/ground net, will influence the spacing
rule within its surroundings  any wire that is X um away from
the fat wire needs to be at least Y um away from any other
geometry.
– Example: fat wire with thin tributaries
• bigger spacing around every wire within certain distance of the thin
tributaries
• ECO insertion of a tributary causes complications
• Strange jogs and spreading when wires enter an influenced area
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Example: LEF/DEF 5.5, April 2003
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Example: LEF/DEF 5.5, April 2003
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Routing Rules (3)
• Density
– Grounded metal fills (dummy fill*)
– Via isodensity rules and via farm rules (via layers must be filled
and slotted, have width-dependent spacing rule analogs, etc.)
• Non-rectilinear (-geometry) routing
– X-Architecture: http://www.xinitiative.org/
• Y-Architecture: http://vlsicad.ucsd.edu/Yarchitecture/ , LSI Logic patents
– Landing pad shapes (isothetic rectangle vs. octagon vs. circle),
different spacings (~1.1x) between diagonal and Manhattan
wires, etc.
• More exceptions
– More non-default classes (timing, EM reliability, …)
• Not just power and clock
– >0.25um width may be “wide”  many exceptions
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Routing Rules
• Degrade completion rates, runtime efficiency
• “Postprocessing” likely no longer suffices
– E.g., antennas
• Can (should) (must) routers “natively” address
these issues?
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Other Symptoms: NRE Cost
• Runtimes for mask data prep (MDP), mask write,
mask inspection
– NRE cost  runtimes  shapes complexity
Context-dependent
fracturing
P. Buck, Dupont Photomasks, July 2001
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Other Symptoms: BEOL Yield
• More than half of catastrophic yield loss is in BEOL
• Copper is deposited  can infer yield loss mechanisms
– Open faults (3x more prevalent than short or bridging faults)
– High-resistance via faults
– Cf. “non-tree routing” for reliability and yield?
• Huge amount of variability budget is in planarization
– Copper is soft  dual-material polish mechanisms
– Oxide erosion and copper dishing  cross-sectional variability,
inter-layer bridging faults, …
• Much, much more…
– Low-k dielectrics: thermal properties, anisotropy, nonuniformity
– Resistivity at small conductor dimensions (grain and barrier
layer effects)
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Density Management and Futures
• Physical model based density rules and fill synthesis
– Current “coevolved” state: Wrong rules, weak tools
W. Grobman, Motorola, DAC-2001
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Evolutionary Paths
• Conflicting goals
– Designer: “freedom”, “reuse”, “migration”
– EDA: “maintenance mode”
– Process/foundry: “enhance perceived value”
(= add rules)
–  Prisoner’s Dilemma
• Fiddling: Incremental, linear extrapolation of
current trajectory
– “GDS-3”
– Thin post-processing layers (decompaction, RET
insertion, …)
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DAC-2003 Nanometer Futures Panel:
Where should extra R&D $ be spent?
Variability/Litho/Mask/Fab
Power Delivery/Integrity
Low Power/Leakage
Tool/Flow Enhancements/OA
IP Reuse/Abstraction/SysLevel Design
P&R and Opt
DSM Analysis
Others (Lotto)
100%
80%
60%
40%
20%
0%
Intel
IBM
Synopsys
TUEMagma
Cadence
STMicro
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Co-Evolutionary Paths
• Designer, EDA, and process communities cooperate
and co-evolve to maintain the cost (value) trajectory of
Moore’s Law
– Must escape Prisoner’s Dilemma
– Must be financially viable
– At 90nm to 65nm transition, this is a matter of survival for the
worldwide semiconductor industry
• Example Focus Areas:
–
–
–
–
–
–
Manufacturability and cost/value optimization
Restricted layout
Intelligent mask data prep
Analog rules
(Layout and design optimizations)
Disclaimer: Not a complete listing
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Basic Goals
• Bidirectional design-manufacturing data pipe
– Fundamental drivers: cost, value
• Pass functional intent to mask flow
– Example: RET for predictable circuit performance, function
– RETs should win $$$, reduce performance variation
–  cost-driven, parametric yield constrained RET
• Pass limits of mask flow up to design
– Example: avoid corrections that cannot be manufactured or
verified
N.B.: 1998-2003 papers/tutorials: http://vlsicad.ucsd.edu/~abk/TALKS/
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Outline
• The Problem, Scope and Goals
• Example: Cost-Driven RET
• Example: Intelligent MDP
• Example: Analog Rules, Restricted Layout, …
• Conclusions
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Design for Value*
•
Mask cost trend  Design for Value (DFV)
Design for Value Problem:
Given
•
•
•
•
Performance measure f
Value function v(f)
Selling points fi corresponding to various values of f
Yield function y(f)
Maximize Total Design Value = i y(fi)*v(fi)
[or, Minimize Total Cost]
•
Probabilistic optimization regime
* See "Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer
VLSI", IEEE ASIC/SoC Conference, September 2002, pp. 411-415.
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Obvious Step: Function-Aware OPC
• Annotate features with “required amount” of OPC
– E.g., why correct dummy fill?
– Determined by design properties such as setup and hold
timing slacks, parametric yield criticality of devices and
features
• Reduce total OPC inserted (e.g., SRAF usage)
– Decreased physical verification runtime, data volume
– Decreased mask cost resulting from fewer features
• Supported in data formats (OASIS, IBM GL-I)
– Design through mask tools need to make, use annotations
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Cost-Driven RET
• MinCorr (DAC-2003): Different levels of RET =
different levels of CD control
Type of
OPC
Aggressive
Medium
No OPC
Ldrawn
(nm)
130
130
130
CD studies due to D. Pramanik, Numerical
Technologies, December 2002
3 of
Ldrawn
5%
6.5%
10%
Figure Delay (, ) for
Count
NAND2X1
5X
(60.7, 7.03)
4X
(60.7, 7.47)
1X
(60.7, 8.79)
OPC solutions due to K. Wampler,
MaskTools, March 2003
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Performance Measure = Delay
Selling point delay = circuit delay which
achieves desired level (say 99%) of parametric
yield
Goal: Achieve selling point delay with minimum
cost of RET’s (OPC)
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MinCorr: The Cost of Correction
DFV Problem
Given: Admissible levels of correction for each
layout feature and the corresponding delay
impact (mean and variance)
Find: Level of correction for each layout feature
such that a prescribed selling point delay is
attained
Objective: Minimize total cost of corrections
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Statistical Timing Analysis
Statistical STA (SSTA) provides PDFs of arrival
times at all nodes
A
Arrival
time
B
Gate delay
C
Arrival
time
Propagate arrival time distribution
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Variation Aware Library Model
• Capacitance and delay values replaced by (,) pair
• Sample variation aware .lib
pin(A) {
direction : input;
capacitance : (0.002361,0.0003);
}
…
timing() {
related_pin : "A";
timing_sense : positive_unate;
cell_rise(delay_template_7x7) {
index_1 ("0.028, 0.044, 0.076");
index_2 ("0.00158, 0.004108, 0.00948");
values ( \
“(0.04918,0.001), (0.05482,0.0015), (0.06499,0.002)",
….
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Generic Cost of Correction
Methodology
Nominally Correct SP&R
Netlist
Min. Corrected
Library
SSTA
Yield
Target met
?
N
Correction
Algorithm
SSTA
Y
EXIT
All Correction
Libraries
• Statistical STA (SSTA)
provides PDFs of arrival
times at all nodes
• Assume variation aware
library models (for
delay) are available
All Correction
Libraries
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Generic Cost of Correction
Methodology
Nominally Correct SP&R
Netlist
Min. Corrected
Library
SSTA
Yield
Target met
?
N
Correction
Algorithm
SSTA
Y
EXIT
All Correction
Libraries
All Correction
Libraries
• Statistical STA (SSTA)
provides PDFs of arrival
times at all nodes
• Assume variation aware
library models (for
delay) are available
• Statistical STA currently
has runtime and
scalability issues
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MinCorr: Parallels to Gate Sizing
• Assume
– Gaussian-ness of distributions prevails
  + 3 corresponds to 99% yield
– Perfect correlation of variation along all paths
 Die-to-Die variation
 1+2 + 31+2 = 1 + 31 + 2 + 32
• Resulting linearity allows propagation of (+3) or
99% (selling point) delay to primary outputs using
standard Static Timing Analysis (STA) tools
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MinCorr: Parallels to Gate Sizing
MinCorr
Gate Sizing Problem:
delay (+k)
costs of correction
Given allowed areas and corresponding delays of each cell,
minimize total die area subject to a cycle time constraint
selling point delay
cost of OPC
Gate Sizing
Cell Area
Nominal Delay
Cycle Time
Die Area





MinCorr
Cost of correction
Delay (+k)
Selling point delay
Total cost of OPC
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Components of MinCorr Sizing
• A yield-aware library that captures
– Delay mean and variance for each library master for
each level of correction
– Relative cost of OPC for each master corresponding to
each level of correction
• Use standard off-the-shelf logic synthesis tool to
perform sizing
– Can use well-tested sizing methods
– Practical runtimes
– Can handle interesting variants, e.g., cost-constrained
selling point delay minimization
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MinCorr: Yield Aware Library
Characterization
Mask cost is assumed proportional to number of
layout features
Monte-Carlo simulations, coupled with linear
interpolation, are used to estimate delay variance
given the CD variation
We generate a library similar to Synopsys .lib with
(+3) delay values for various output loads
Cost modeled by relative figure count multiplied by the
number of transistors in the cell
Gate input capacitance variation with CD
considered
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Experiments and Results
Synopsys Design Compiler used as the synthesis tool
to perform “gate sizing”
Figure counts, critical dimension (CD) variations
derived from Numerical Technologies OPC tool*
Use a restricted TSMC 0.13 m library
7 cell masters: BUF, INV, NAND, NOR
Approach tested on small combinational circuits
alu128: 8064 cells
c7552: 2081 cell ISCAS85 circuit
c6288: 2769 cell ISCAS85 circuit
*Courtesy Dipu Pramanik, NTI
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Yield Library Generation
Type of
OPC
Aggressive
Medium
No OPC
Ldrawn
(nm)
130
130
130
3 of
Ldrawn
5%
6.5%
10%
Figure Delay (, 3)
Count for NAND2X2
5X
(64.82, 2.14)
4X
(64.82, 2.80)
1X
(64.82, 4.33)
Sample Result of Library Generation
• Three levels of OPC considered
• Input slew dependence ignored
• Interconnect variation ignored
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Cost Savings with MinCorr Sizing
Design
Normalized Cost
alu128
5.0 (Aggressive OPC)
Normalized Selling
Point Delay
0.9644
4.0 (Medium OPC)
1.0 (No OPC)
1.0657
1.0119
0.9739
1.0000
0.9644
0.9976
5.0
4.0
1.0
0.9432
0.9621
1.0000
1.4639
1.2079
5.0
0.9432
0.9848
0.9480 Andrew Kahng – June 2003
c7552
c6288
42
Cost Savings with MinCorr Sizing
Small (~5%) selling point delay variation
between max- and min-corrected versions of
design (5X difference in cost)
Sizing-based optimization achieves 17-79%
reduction in OPC cost without sacrificing
parametric yield
Andrew Kahng – June 2003
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Outline
• The Problem, Scope and Goals
• Example: Cost-Driven RET
• Example: Intelligent MDP
• Example: Analog Rules, Restricted Layout, …
• Conclusions
Andrew Kahng – June 2003
44
MDP for Minimum NRE
• Mask data prep (MDP)
– Partition layout shapes into multiple gray-scale writing passes
– Determine apertures, beam currents, dwell times, shot ordering, …
– Write error X MEEF gives wafer CD error
• Examples:
– Simplified write of diagonal lines when triangular aperture is available
– Raster vs. Vector write
– Major field layout, subfield scheduling, …
• Driven by performance analyses, sensitivities, costs
• Many other manufacturing NRE optimizations available
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Example: Triangular Apertures
www.xinitiative.org
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Subfield Scheduling (SPIE Microlithography’03)
• Use of high-energy e-beams in mask writing is limited
by resist heating effects (resist distortion, irreversible
chemical changes)
• Corrective measures (lower beam current density,
delays between flashes, “multi-pass” writing, etc.)
reduce throughput
Mask Writing Schedule Problem
Given: Beam voltage, resist parameters, mask write throughput
requirement
Find: Beam current density and subfield writing schedule to
minimize the maximum resist temperature Tmax
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Throughput-Normalized Subfield Scheduling
Max
48.85C
Mean
27.59C
Sequential schedule
Max
37.24C
Mean
20.37C
Lagarias schedule
Max
32.68C
Mean
16.07C
Max
40.49C
Mean
16.97C
Random schedule
Greedy schedule
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Outline
• The Problem, Scope and Goals
• Example: Cost-Driven RET
• Example: Intelligent MDP
• Example: Analog Rules, Restricted Layout, …
• Conclusions
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Analog Rules
• We don’t need no $#(*&(! “rules”
– Rules just make lithographers feel better (?)
• Ultimately, bottom line is cost of ownership, TCOG
• Given adequate models of MDP, RET and Litho flows,
design tools can and should optimize parametric yield,
$/wafer, profits
– More examples: critical-area reduction by decompaction,
introducing redundancy (vias, wires), …
• Automated learning of models and “implicit rules”
– Current approach: test wafers, test structures, second-hand
understanding
– S. Teig, ISPD-2002 keynote: machine learning techniques
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Restricted Layout
• “Soft reset” = 1-time hit on Moore’s Law density scaling
• Restricted Design Rules (“RDR”) can be compensated many ways
– embedded 1-T SRAM fabric, stacking, I/O circuit design, …
– N.B.: Moore’s Law is a “meta” Law!
Dual Exposure Result
Islands
Checkerboard
0
Example:
PhasePhirst!
(Levenson et al.)
180
Transparent
180 Phase Shifters
0
Opaque
Trim Mask Exposure
First Exposure
Dark-Field PSMs
or
M. D. Levenson, 2003
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Pre-Made Mask Blanks
• PhasePhirst!
– Levenson/Petersen/Gerold/Mack, BACUS-2000
• Idea: mask blanks can be mass-produced and stored
to reduce average cost (e.g., $10K), then customized
on demand
 0


 0
0
0
M. D. Levenson, 2003
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Notes on Regular Layout
• 65 nm has high likelihood for layouts to look like regular gratings
– Uniform pitch and width on metal as well as poly layers
–  Predictable layouts even in presence of focus and dose variations
• More manufacturable cell libraries with regular structures
• New layout challenges (e.g., preserving regularity in placement)
• Caveats
– Non-minimum width poly is less susceptible to variation  larger devices
(with same W/L) may lead to more robust designs (so, selective “upsizing”
may be an alternative to regular layouts)
– 180nm node is a “sweet spot” for cost, analog/mixed-signal integration,
etc.  more and more technology nodes will tend to coexist
Andrew Kahng – June 2003
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Outline
• The Problem, Scope and Goals
• Example: Cost-Driven RET
• Example: Intelligent MDP
• Example: Analog Rules, Restricted Layout, …
• Conclusions
Andrew Kahng – June 2003
54
Conclusions
• Designer, EDA, and mask communities must cooperate
and co-evolve to maintain the cost (value) trajectory of
Moore’s Law
– Wakeup call for supplier industries: Intel skipping 157nm litho
• Basic goal: bidirectional design-mask data pipe
– Drivers: cost, value
– Pass functional intent to mask flow
– Pass limits of mask flow up to design
• Example focus areas (not a complete listing!)
–
–
–
–
–
Manufacturability and cost/value optimization
Restricted layout
Intelligent mask data prep
Analog rules
(Layout and design optimizations)
Andrew Kahng – June 2003
55