Transcript Presentation 5 - J

Nano and Giga Challenges in Microelectronics
Symposium and Summer School
Research and Development Opportunities
Cracow
Sep. 13-17, 2004
Afternoon 4: Carbonanotubes and Molecular Electronics (3:00pm-6:15pm), Mon., Sep. 13th, 2004
Electrostatic Characteristics of
Carbon Nanotube Array Field
Effect Transistors
Yiming Li, Jam-Wem Lee, and Hong Mu chou
Department of Computational Nanoelectronics, National Nano Device Laboratories
Microelectronics & Information Systems Research Center, National Chaio Tung University
Department of Electrophysics, National Chaio Tung University
1001 Ta-Hsueh Rd., Hsinchu 300, Taiwan
Introduction
 Carbon nanotube (CNT) field effect transistors (FETs) with
promising nanoscale device characteristics have recently been
explored
 For ultrasmall nanoscale FETs, CNT FETs have provided
fascinating characteristics by comparing with silicon-based
metal-oxide-semiconductor FETs (MOSFETs)
 For CNT FETs with a planar bottom gate electrode
configuration, the CNT is un-passivated
 The larger thickness of the back gate dielectric and the lower
dielectric constant of the air surrounding the CNT result in a
small gate-to-nanotube capacitance and produce the lower onstate current
Introduction
 For the top gate geometry, the CNT is covered by a gate
insulator and demonstrates several advantages over the case of
bottom gate, such as lower operating voltage due to stronger
coupling between the gate and the nanotube, and more flexibility
to control individual devices
 For CNT FETs with a wrap around gate, the CNT is surrounded
by a cylindrical gate and this coaxial structure exhibits the
strongest capacitive coupling between the gate and the tube
 Among these three structures, it is known that single CNT can
only contribute little driving current, array of CNT has been
considered as a candidate to improve the electrical
characteristics and physical properties (e.g., driving capability)
of CNT FETs
Introduction
 For a CNT array, the screening of the charge induced by CNTs
significantly affects the structure’s electrostatic characteristics,
such as capacitance, in particular when many CNTs are in close
proximity
 A unified investigation on the electrostatic characteristics with a
multidimensional electrostatic simulation will clarifies the main
difference among various CNT FET arrays and benefits the
design and fabrication of CNT FET devices
 We in this paper study the electrostatic characteristics and the
gate capacitance for a carbon nanotube (CNT) array with three
structures of gate electrode: (1) top gate, (2) wrap around gate,
(3) and bottom gate CNT field effect transistor (FETs).
Introduction
 Taking the structure’s radius and gate length of CNT FET into
consideration, the three-dimensional (3D) electrostatic
simulation and corresponding gate capacitance are calculated
and compared using adaptive finite volume method
 It is found that there is 20% difference in calculating gate
capacitance between 2D and 3D modeling and simulation
 3D simulation shows that a wrap around gate gives the largest
gate capacitance among structures
 A bottom gate possesses the weakest gate controllability
 Results of the 3D electrostatic simulations can also be applied to
estimate the magnitude of on-current of CNT FETs.
Computational Device Structures
Illustration of the three simulated (a) bottom, (b)
top, (c) and wrap around gate structures in the
array of the CNT FET
(a) bottom
(b) top
(c) wrap around
gate structures
Computational Device Structures

A 3D Laplace equation is solved for the studied CNT FETs
structures

The finite volume method is used to discretized the
simulation domain

The adaptive computing technique is applied to perform
the error estimation and mesh refinement

A preconditioned conjugate gradient method is developed
to solve the system of algebraic equations
Results and Discussion
The simulated potential for the (a) bottom, (b)
top, (c) and wrap around gate structures
(a) bottom
(b) top
(c) wrap around
gate structures
Results and Discussion
The gate-to-end-tub (dash line) and gate-to-middle-tube (solid line)
capacitances versus the pitch distance
Wrap around gate
0.35
C (fF / m)
0.30
Top gate
0.25
0.20
0.15
Bottom gate
0.10
0
5
10
Pitch (nm)
15
Results and Discussion
The 3D/2D capacitance ratio vs. pitch distance. The dash and solid
lines are the gate-to-end-tub and gate-to-middle-tub capacitance ratios,
respectively
1.5
Bottom gate
Ratio
1.4
Top gate
1.3
Wrap around gate
1.2
0
5
10
Pitch (nm)
15
Results and Discussion
The gate-to-middle-tube capacitance vs. pitch distance
simulated for the wrap around structure with its gate length from
5nm to 20nm. The right figure shows that the gate-to-end-tube
capacitance vs. pitch distance
0.45
0.44
wrap-middle
wrap-end
0.42
0.40
0.40
0.38
0.30
0.25
L = 20 nm
L = 15 nm
L = 10 nm
L = 05 nm
0.20
0.15
C(fF/um)
C(fF/um)
0.35
0.36
0.34
L = 20 nm
L = 15 nm
L = 10 nm
L = 05 nm
0.32
0.30
0.28
0.26
0.24
0.10
1
pitch(nm)
10
1
10
pitch(um)
Results and Discussion
The gate-to-middle-tube capacitance vs. pitch distance
simulated for the top gate structure with its gate length from 5nm
to 20nm. The right figure is the gate-to-end-tube capacitance vs.
pitch distance
0.35
0.36
top-middle
0.30
0.32
0.30
0.25
0.20
L = 20 nm
L = 15 nm
L = 10 nm
L = 05 nm
0.15
0.10
0.05
1
10
pitch(nm)
C(fF/nm)
C(fF/um)
top-end
0.34
0.28
0.26
0.24
L = 20 nm
L = 15 nm
L = 10 nm
L = 05 nm
0.22
0.20
0.18
0.16
1
10
pitch(nm)
Results and Discussion
The gate-to-middle-tube capacitance vs. pitch distance
simulated for the bottom gate structure with its gate length from
5nm to 20nm. The right figure is the gate-to-end-tube
capacitance vs. pitch distance
0.18
0.18
bottom-end
bottom-middle
0.16
C(fF/um)
C(fF/um)
0.16
0.14
0.12
0.10
L = 20 nm
L = 15 nm
L = 10 nm
L = 05 nm
0.08
0.06
0.14
0.12
L = 20 nm
L = 15 nm
L = 10 nm
L = 05 nm
0.10
0.08
0.04
1
10
pitch(nm)
1
10
pitch(nm)
100
Results and Discussion
The extracted fringing capacitance vs. pitch simulated for both the
top gate and wrap around gate structures
600x10-6
fringing capacitance
C(fF)
500x10-6
400x10-6
300x10-6
top-gate(middle)
top-gate(end)
wrap-gate(middle)
wrap-gate(end)
200x10-6
100x10-6
1
10
pitch(nm)
Conclusions




We have studied the gate capacitance for a CNT array
with three different gate electrode structures: (1) top
gate, (2) wrap around gate, (3) and bottom gate CNT
structures
Taking the structure’s radius and gate length of CNT FET
into consideration, the three-dimensional potential
distribution and corresponding gate capacitance have
been calculated using adaptive finite volume method
It has been found that there is 20% difference in
calculating capacitance between 2D and 3D modeling
and simulation
Results of the 3D electrostatic simulations can also be
applied to estimate the magnitude of on-current of CNT
FETs.
Thank you for your attentions!