Transcript t - Sintesi Logica

Terza giornata nazionale di sintesi logica
A comparison between different logic
synthesis techniques from the digital
switching noise viewpoint
G. Boselli, V. Ciriani, V. Liberali
G. Trucco
Dept. of Information Technologies
Verona, 21 June 2007
Introduction

Mixed-signal integrated systems
Careful modeling of crosstalk between analog and digital
sections
 Disturbances injected by digital circuits can degrade
overall system performance
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
Digital switching
Deterministic process, depending on circuit parameters
and input signals
 Huge number of logic blocks  cognitively stochastic
process
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Digital switching currents as stationary shot noise
process
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Amplitude distribution
Power spectral density
Digital switching current

Proposed model valid under some hypotheses:

Transition activity of a logic gate independent of the
activity of other gates
In fact, gate inputs are driven by other gate outputs
 A large system contains a huge number of gates  each gate
depends on a small number of neighboring cells

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Logic transitions uniformely distributed in time
Correct for asynchronous digital systems
 Synchronous system: transistion activity correlated with clock
 more complex analysis


All logic transitions require the same time  all current
pulses have the same finite time duration
Stochastic model of digital switching noise (1)

Consider:
Asynchronous digital network
 Identical logic cells driving equal capacitive loads
 Switching instants of input signals applied to gates
independent and randomly distributed in uniform
manner
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Digital switching noise as shot noise process

Switching instants of input signals as Poisson points
Stochastic model of digital switching noise (2)
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Input transition of logic gates as Dirac impulses
 Train of impulses, taken at random instants
 X(t): stochastic process representing the input transition of logic
gates
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Logic gates all equal (same IDD and ISS current absorption) 
convolution between train of impulses X(t) and current absorbed
by single logic gate h(t) = total current absorbed by the entire
circuit I(t)
Amplitude distribution of switching noise


Represented by the Probability Density Function (pdf, f(x)) of
the stochastic process I(t)
 Calculated from the pdf of the single current pulse
Arbitrary time instant t1
 pdf of the total current at time t1 depends on the number of
Poisson impulses falling in the interval
and the
pdf of the single current pulse fH(x)
where
Power spectral density of switching noise

Power Spectral Density (psd) of switching current:
where



is
the
psd
of
logic
transition
impulses X(t)
H(f) is the Fourier transform of the impulse response h(t)
h(t): current pulse, approximated with a
triangular pulse  the charge Q
transferred during the complete switching
of a logic gate is equal to the area under
the curve
Normalized power of switching current

As a result of few calculations, we obtain
whose normalized power is

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Term
: dc component of digital switching power

Term
: ac component of the power
More general expression:

: “pulse shape” factor, depending on the single current
pulse waveform in time domain.
Model validation

clip.pla: digital combinatory circuit included in the IWLS’93
benchmarks
synthesized using equal-delay gates in a 180-nm CMOS
technology: inverter, 2-input NAND and NOR gates.
 network made of about 130 logic gates.
 inputs are driven with random digital signals; at any time, only
one bit can change its logic value.


Transistor-level simulation with SPECTRE
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values of the iDD current, sampled at 1-ps intervals, were
stored for post-processing.
Two different average values of input transition rates, giving a
low-density and a high-density switching activity.

the number of logic transitions at high-density transition is
approximately ten times larger than the low-density transition.
Model validation: amplitude distribution
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Current waveforms exhibit triangular pulses
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Simulated circuit gates with different capacitive loads  different current
peaks (generalized Poisson process).

Amplitude density constant for intermediate values of current
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For low current values the amplitude density is larger to account for pulse
tails.

Peak values of the single current pulse assumed to be uniformly distributed
between i2 and i3.
Amplitude density of the single switching
current pulse.
Digital switching currents
(low density of logic transitions).
Amplitude distribution: results
Simulated pdf of the iDD switching current (low and high density of logic transitions)
Theoretical pdf of the iDD switching current (low and high density of logic transitions)
Model validation: power spectral density
Simulated psd of the iDD switching current (low and high density of logic transitions)
Theoretical psd of the iDD switching current (low and high density of logic transitions)
IDEA

To analyze different logic synthesis techniques
from digital switching noise viewpoint


To apply the developed methodology to the same logic
function, synthesized with different techniques
CLIP benchmark circuit:
Sop: ~ 770 MOS transistors
 Xor: ~ 400 MOS transistors

6 transistors
16 transistors
SOP subcircuits
INVERTER
NAND
NOR
XOR circuit

A B
Y
0 0
B
0 1
B
1 0
A
1 1
0
XOR asymmetric circuit
just in one case the output is connected to a supply node
 In the other three cases XOR works as transfer gate
 Differences which depends on what input signal switches
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Power dissipation
fewer MOS transistor= lower digital switching noise?
 MOS transistor:
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Static power dissipation
 Dynamic power dissipation
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It is important the number and the distribution of
input signal commutation
Input files
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Switching at random instants
At any time just one input signal can commutate
Currents
SOP
XOR
PDF
SOP
XOR
PSD
SOP
XOR
Conclusion
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Digital switching noise as stochastic process

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Faster estimation of digital switching noise, described by few
parameters
Digital switching current as shot noise process
Amplitude density and power spectral density of switching
currents derived
Circuit synthesized with XOR gates exhibits lower switching
activity
Future development
 Analysis for pseudo-synchronous circuits
 Methodology to optimize the number and distribution of the
commutations of logic gates