Transcript Photo-acoustic Imaging

Dynamic Power
Consumption In Large FPGAs
WILLIAM GARCIA,
ANDREW MORTELLARO
Literature Survey

L. Shang , A. S. Kaviani and K. Bathala "Dynamic power
consumption in Virtex-II FPGA family", Proc. ACM/SIGDA 10th Int.
Symp. FPGA, pp.157 -164 2002
Introduction

Recent advances in semiconductor process technology has led to
rapid scaling of transistor dimensions

High density of transistors on the same chip has made power
consumption one of the major challenges of deep submicron IC design

Need to identify utilized logic and routing resources that contribute
to the dynamic power consumption
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Goals of the paper:
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Better understanding of where power is consumed in FPGAs

Use this understanding to help expert designers reduce or control the
power characteristics of their design
Related Work
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FPGA-specific power studies lagging behind those of ASIC
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Recent studies:
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Power distribution of the Xilinx 4000 family
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Power dissipation of FPGA interconnection
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
Manhattan distances between logic blocks
This study
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Consideration of state-of-the-art FPGA
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
More accurate results
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Advanced process technology and reduced power supply
Access to detailed schematics of FPGA circuits
Larger circuits tested
Background
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What is in an FPGA?
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Look-Up Tables (LUTs)
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Element in Block Ram (BRAM) that represents a simple logic circuit
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Combinational logic element
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BRAM is indexed by inputs to LUT
Flip-Flops
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Sequential logic element
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Can be connected to LUT output
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Groups of LUT’s and flip-flops called slices
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Slices can be combined to form Complex Logic Blocks (CLB’s)
The Routing Matrix
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Responsible for connecting CLB’s to rest of FPGA
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Consists of switch boxes and multiplexors
Virtex-II Family
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Legacy Device
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Most of the area is utilized by the programmable fabric
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Paper focuses solely on fabric power consumption
Each Configurable Logic Block (CLB) contains 4 slices
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The fabric contains a segmented routing structure
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Each slice contains two LUTS and two FFs
2 CLB (doubles), 6 CLB (Hexes), and cross-chip (Longs)
Two sets of switches at the inputs and outputs of CLBs
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Input Crossbar (IXbar) and Output Crossbar (OXbar)
Power Consumption
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Static Power (caused by leakage current)
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Due to subthreshold channel conduction
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Very important for large future designs, but only dynamic power is considered here
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
Subthreshold channel current of a transistor exponentially increases with any Vth decrease
Dynamic Power (caused by signal transitions)
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Largest cause is charging/discharging of capacitance
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Additional cause is short-circuit power (less than 10%)

Due to switching of inverters in the buffers
Virtex-II power consumption is 5-20% static power
 Three main factors of total power dissipation
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
Effective Capacitance, Resource Utilization, and Switching Activity
Effective Capacitance
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Power Measurements
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Target resource is added to reference circuit to calculate power difference
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Linear relationship between frequency and power insures correctness
Spice Simulation
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Needed because some resources not easily isolated
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Using Cadence and Hspice transistors are simulated from vendor schematics
Results
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Found for device 2v1000FG256-5
Resource Utilization
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Large designs are only used in this case study
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The routed design is available in a NCD format
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This is used for power estimation
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Xilinx tools convert NCD binary to text format
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Perl programs convert text format to resource utilization metrics
Switching Activity
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Most difficult to analyze; dependent on input patterns
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Random inputs were mostly used
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Two activities contribute to switching activity
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Nets
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One source and multiple destinations
Logic
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Occurs inside the LUT
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Modeling is used to calculate switching activity
Results (1/2)
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Input Stimuli
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Next best thing to real input
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Large benchmark circuit
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90% area of 2V3000 with 14336 slices
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Flip-flop count as high as 85% the LUT count
Random Inputs
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Restricts the choice of benchmark circuits
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Used a set of designs for benchmarking
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FIR, FFT filters; DES encryption; multiplier circuits
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Utilizes 7790 slices with 13276 LUTs and 2483 flip-flops
Two cases:
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Random input supplied every five cycles
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Random input supplied every cycle
V = supply voltage
f = operating frequency
Ci = effective capacitance
Ui = utilization
Si = switching activity
Results (2/2)
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All
Real Input Stimuli
Switching Activity
Random Input Stimuli
High Switching Activity
Conclusion
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Power estimation in FPGAs depend on three factors:
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Effective capacitance
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Resource Utilization
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Large reference designs were tested against for a standard analysis
Switching activity
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Obtained by measurement and SPICE simulations
Study considered a variety of input patters for various benchmarks
Shortcomings and Opportunities
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Power estimation for newer Virtex devices
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Tradeoffs between using large or small designs
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More varied or realistic input patterns for switching measurements