Transcript Center for Integrated Systems Design

VLSI Design and Test Automation
Research
F. Beyette, H. Carter, W. B. Jone,
C. Purdy, K. Tomko, R. Vemuri, P. Welsey
Focus
• Design, analysis, and test of integrated
circuits and systems.
• Digital, analog, mixed signal and mixed
technology microchips and systems.
• Applications to computing, communication,
and embedded processing.
• VLSI systems education.
SYSTEM
MODULE
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GATE
CIRCUIT
DEVICE
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Existing Research Strengths
• Design
– Digital and analog microchip design
– FPGA-based reconfigurable systems
– Mixed signal, mixed technology systems
(opto-electro-mechanical microsystems)
– Test architectures, design-for-testability
– Low power design
• Design Automation and CAD
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Automated design synthesis
Discrete and continuous simulation
Test pattern generation
Analysis, benchmarking, experiment design
Hardware description languages, VHDL
Distributed/parallel computing and CAD methods
We are working very hard !
Result
Visibility and Impact
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150 journal, 410 conference papers since 90
3 books and 30 book chapters
7 Best Paper awards
Editorships
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IEEE Transactions on VLSI
IEEE Potentials
Transactions on Modeling and Simulation
Journal of VLSI Design
IEEE Computer (guest)
• General/program/panel chairs of numerous
conferences (30 since 95)
Industry Employers of Our Graduates
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Intel
Xilinx
Motorola
Hewlett-Packard
Honeywell
Sun Microsystems
LSI Logic
Digital-Compaq-Intel
Lucent
AT & T
Qualcom
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Cadence
Synopsys
Mentor Graphics
NeoLinear
FTL Systems
Simplex
Matrix
Symbios
Fore Systems
Oracle
Microsoft
EDAptive
• 45 PhDs and 120 Masters graduated since 1990.
• 30 PhDs and 45 Masters in progress.
Past Sponsors of Our Research
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DARPA (MTO, ITO, DSO)
AFRL (SN, IF, and Mantech at WPAFB and GAFB)
Semiconductor Research Corporation
National Science Foundation
National Security Agency
DAGSI
NASA
Industries (GE, TI, Xilinx, TRW, Raytheon, Sun,
MTL, FTL, EDAptive….)
• Several SBIRs (8 Phase II and many more Phase I)
Total $15M since 1990.
Government Lab Collaborators
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Sandia National Lab
NASA Langley
NASA Lewis
AFRL, Sensors Directorate
AFRL, Information Directorate
Rome Research Institute, GAFB
JPL
Educational Grants/Contracts
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NSF (VLSI minor program and VLSI Design and Test Lab)
NSF (combined research and education)
DARPA (RASSP educator and facilitator contract)
DARPA (ADA education)
Several graduate fellowships (SRC, OBR etc.)
MOSIS (About 10K/year since 1991 for microchip
fabrication. About 250 microchips, each with 15,00020,000 transistors, were fabricated and tested.)
• Xilinx (hardware donations, over $300K)
• Altera (hardware and software donations)
• Cadence, Synopsys, Xilinx etc. (CAD software donations
worth several $M)
Multichip Synthesis
• How to partition a large
specification and synthesize
a multichip design using the
available package options?
Die and package options.
Multichip Synthesis System, MSS
• Viper multichip module design was
automatically synthesized using
the MSS CAD system.
• Viper is a RISC microprocessor.
• To accomplish this, the MSS system
was successfully integrated with
many commercial CAD systems.
VASE Mixed Signal Synthesis System
Functional Specification
in VHDL-AMS
Analog Component
Library
Performance Goals
Analog/Digital
Partitioning
Analog
Synthesis
Analog Layout
• VASE research
nominated for Best Paper
Award at DATE’99
Digital Component
Library
Digital
Synthesis (DSS)
Layout
Integration
Digital Layout
Mixed Analog-Digital
Layout
Multi-Channel Voice Transmitter-Receiver
Synthesized Using VASE
A Plugin Architecture for Linking
CAD Tool Backends to a VHDL
Frontend
Philip A. Wilsey
Experimental Computing Lab
SAVANT
VHDL '93
VHDL-AMS
VHDL-2001
TyVIS
Compliant C++
TyVIS VHDL
Simulation
Kernel
WARPED
Simulation
Kernel
MPI/TCP/BIP
Scram
VHDL
Analyzer
IIR
Transmogrifi
er
Cloned
IIR
SAVANT
IIR
w/ TyVIS C++
Code Generator
SAVANT
Cloning Step
w/ TyVIS extension
(Reduced Form)
SAVANT
SAVANT: VHDL analyzer/code generator
TyVIS: C++ Code Generator & VHDL simulation kernel
WARPED: Discrete-event simulation kernel
Extension by Inheritance
IIRBase
IIRBase
Extended for
new backend
analysis purposes
IIRScram
IIRScram
IIR
IIRExtension
IIR
Extensibility through Cloning
VHDL
Source
SAVANT
Analyzer
AIRE
Library
Form
Cloning
Step
Plugin
Extended
AIRE
Plugin
Output
The Clone Step
IIR_ArchitectureDecl
aration
scram
IIR_TextLitera
l
scram
IIR_Statemen
tList
scram
IIR_ProcessState
ment
IIR_ProcessState
scram
ment
IIR_ProcessState
scram
ment
scram
IIR_ArchitectureDecl
aration
publish_xml
IIR_TextLitera
l
publish_xml
Module-Loaded
Factory
IIR_Statemen
tList
publish_xml
IIR_ProcessState
ment
IIR_ProcessState
publish_xml
ment
IIR_ProcessState
publish_xml
ment
publish_xml
Prof. C. Purdy-- Digital Design Research
1. Sensor data processing and systems-on-a-chip
--Improved accuracy
and speed
--Smaller circuits
2. Evaluation of CAD algorithms
Circuits & Systems Design Laboratory
Network on Chip (NoC)
• On chip communication with a network is very simple
and reliable
• Routers are used to direct
the flow of communication
• Predictable electrical
parameters enable
high performance circuits
• Enables the use of fault tolerant wiring and
protocols
• Facilitating reuse with a universal interface and also
extending the reuse to network
MEMS BIST and BISR
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2.
Research Goals:
Develop robust and efficient BIST solution for capacitive MEMS
Implement redundancy built-in self-repair feature into MEMS device,
thus greatly enhance the yield rate and in-field reliability
BISR comb accelerometer
Mites crawl on MEMS gears
Capacitance partition of
dual-mode BIST solution
Importance of Embedded Memory Testing / Diagnosis /
Repair
Source – ITRS 2001 – Percentage of Logic Forecast in SoC Design
Year
Node
(nm)
% Area
New Logic
% Area
Reused
Logic
% Area
Memory
1999
2002
2005
2008
2014
180
130
100
70
35
64
32
16
8
2
16
16
13
9
4
20
52
71
90
94
Interconnect Noise Testing for HighSpeed Deep sub-Micron VLSI circuits
• Deal with signal integrity problem due to
cross-coupling capacitance and inductance in
long interconnects
• Circuit speed in the level of GHZ
• Hard to accurately model the behavior of
coupling capacitance and inductance for
deep-submicron, high-speed (GHZ) circuits
• Try to use pseudo-exhaustive built-in self-test
to solve the problem