Transcript PresentationNSS_Ballabriga - Indico

NSS-MIC 2009 Summary
Rafael Ballabriga
PH-ESE-ME
NSS Conference
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Photodetectors and Scintillation detectors
Semiconductor Detectors
Analog and digital circuits
Nuclear measurements and monitoring techniques
New detector concepts and instrumentation
Instrumentation for homeland security
Data acquisition and analysis systems
Radiation damage effects
Computing and software for experiments
Trigger and front-end systems
Gaseous detectors
High energy physics instrumentation
Gamma ray imaging
Neutron Imaging
Accelerators and beam line instrumentation
NSS-MIC conference, Orlando (October 2009)
R. Ballabriga
MIC Conference
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X-Ray imaging
PET/SPECT instrumentation
Simulation and modelling of medical imaging systems
Animal imaging and instrumentation techniques
Image processing and evaluation
Image reconstruction
Quantitative imaging techniques
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This talk
• ASICS
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PX90DC (P. Grybos, AGH UST Cracow)
Medipix3 (R. Ballabriga, CERN)
ASIC for SDD-based X-ray Spectrometers (G. De Geronimo, BNL)
New dynamic TOT method (K. Shimazoe, Tokio University)
• 3D Interconnects
– 3D IC @ Fermilab (G. Deptuch, Fermilab)
– New techniques in SOI pixel detectors (Y. Arai, KEK)
– MAPS based on 3D integration (W. Dulinski, IPHC Strasbourg)
• SiPM
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2 posters/~250 in NSS-2006
15 posters/~250 in NSS-2009 (and a few talks)
Introduction
SPIROC chip (W. Shen, Heidelberg)
BASIC chip (C. Marzocca, Politecnico di Bari and INFN)
Readout of SiPM for TOF PET (P. Jarron, CERN)
• Summary
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ASICs
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PX90DC (P. Grybos)
Prototype readout
chip for hybrid pixel
detector
Functionaliy: Single
Photon Counting,
Energy window,
continuous readout
90nm CMOS
technology (TSMC)
9 metal layers
40x32 pixels
100umx100um pixel
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PX90DC (P. Grybos)
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Characterization of the
Medipix3 Pixel Readout Chip
R. Ballabriga, M.Campbell, E. H. M. Heijne, J.
Jakubek, X. Llopart, R. Plackett, S. Pospisil,
L. Tlustos, Z. Vykydal, W.Wong
CERN, PH department
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Medipix3 Introduction
• Medipix3 is a Hybrid Pixel Detector readout chip
working in Single Photon Counting Mode
• Designed in 130nm CMOS technology
• Highly configurable pixel
• Flexible readout scheme (ROI, Configurable output
port width)
• It implements a novel architecture for improving the
system’s spectrometric performance
Eliminating the distortion from charge diffusion in
the spectrum
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Charge summing and allocation concept
The winner takes all
• Charge is
• The incoming
summed in
quantum is
every 4 pixel
assigned as a
cluster on an
single hit
event-byevent basis
55µm
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Medipix3 Pixel Schematic
A B C
D E F
G H I
BLOCK DIAGRAM OF PIXEL E
Clk_read
Conf
CF
From adjacent
pixels (F, H, I) x6
From adjacent
pixels (A, B, D)
x3
x2
gm
VFBK
CTEST
x3
x1
TestBit
Test
Input
PolarityBit
GainMode
SummingMode
B_TH1<0:4>
TH2
x1
DISC
Previous
Pixel_B ShutterB
x1
x1
Cluster
common
control
logic
+
Arbitration
circuitry
x1
CounterA
x1
CounterB
x1
x1
Next Pixel_A
x1
Next Pixel_B
B_TH2<0:4>
ModeContRW
DisablePixelCom
AdjustTHH
pixels (A, B, D)
SpectroscopicMode
x6 To adjacent
x6
To adjacent
pixels (F, H, I)
ANALOG
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ShutterA
x1
DISC
x1
gm
Previous
Pixel_A
x6
TH1
Input
Pad
CounterSel
x1
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DIGITAL
R. Ballabriga
Pixel Layout
• Design in 130 nm CMOS technology, 8 metal layers
• ~1600 transistors per pixel
7
1. Preamplifier
2. Shaper
5
3. Two discriminators with 5-bit
4
1
2
3
4. Pixel memory (13-bits)
55 µm
6
threshold adjustment
5. Arbitration logic for charge
allocation
6. Control logic
7. Configurable counter
55 µm
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Medipix3 chip
Pixel matrix of 256 x 256 pixels
Bottom periphery contains:
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Top periphery contains:
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Power/Ground pads
TSV landing pads
Pads extenders
> 115 Million transistors
Typical power consumption:
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LVDS drivers and receivers
Band-Gap and 25 DACs (10 9-bit and 15
8-bit)
32 e-fuse bits
EoC and 2 Test pulse generators per pixel
column
Temperature sensor
Full IO logic and command decoder
Power/Ground pads
TSV landing pads
Pads extenders
17.3 mm
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600 mW in Single pixel mode
900 mW in Charge summing mode
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14.1 mm
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Medipix3 Modes of Operation
System Configuration
Pixel Operating Modes
# Thresholds
Single Pixel Mode
Fine Pitch Mode → 55 µm x 55 µm
Spectroscopic Mode → 110 µm x 110 µm
Front-end Gain Modes
Single Cluster Mode
Charge Summing Mode
Linearity
High Gain Mode
~10 ke-
Low Gain Mode
~20 ke-
Pixel Counter Modes
2
8
# Thresholds
2
Dynamic range
# Counters
1-bit
1
2
4-bit
15
2
12-bit
4095
2
24-bit
16777215
1
# Active Counters
Dead Time
Sequential Read-Write
2
Yes
Continuous Read-Write
1
No
Pixel Readout Modes
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Charge Summing Mode
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Electrical Measurements
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Threshold scan with a 109Cd source
(preliminary)
20000
18000
Total Chip Counts
16000
Ideal
14000
12000
10000
8000
6000
4000
2000
0
0
20
40
60
80
100
120
140
160
180
200
Threshold (DAC steps)
Threshold scan with a 109Cd source (Shutter time 2.5s)
2 peaks expected (~22kev and ~25kev)
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Threshold scan with a 109Cd source
(preliminary)
20000
18000
Ideal
SPM
Total Chip Counts
16000
14000
12000
10000
8000
6000
4000
2000
0
0
20
40
60
80
100
120
140
160
180
200
Threshold (DAC steps)
Threshold scan with a 109Cd source (Shutter time 2.5s)
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Threshold scan with a 109Cd source
(preliminary)
20000
18000
Ideal
SPM
CSM
Total Chip Counts
16000
14000
12000
10000
8000
6000
4000
2000
0
0
20
40
60
80
100
120
140
160
180
200
Threshold (DAC steps)
Threshold scan with a 109Cd source (Shutter time 2.5s)
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Measured X-ray tube spectrum (preliminary)
20000
deriv(Num of Chip Counts)
18000
16000
CSM_Ni_HV50
14000
12000
10000
8000
6000
4000
2000
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0
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100
150
200
250
300
350
Threshold (DAC steps)
Spectrum of a W X-ray tube at 50kV and I=10mA.
~2mm Al prefiltering. Ni foil filtering. (8.3keV K-edge)
0.5s exposure time
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Summary of electrical measurements
Single Pixel Mode
Charge Summing Mode
11.4 mV/ke-
CSA Gain
CSA-Shaper Gain
Non-Linearity
Peaking time
Return to baseline
Electronic noise
Unadjusted Threshold spread
Expected Minimum threshold
Pixel power consumption
High Gain
34 nA/ke-
Low Gain
20 nA/ke-
High Gain
<5% up to 10 ke-
Low Gain
<5% up to 20 ke-
HG / LG
~110 ns
High Gain
<1.5 µs for 12 ke-
Low Gain
<2.5 µs for 25 ke-
High Gain
~60 e-rms
~130 e-rms
Low Gain
~85 e-rms
~180 e-rms
High Gain
~1000 e-rms
~1800 e-rms
Low Gain
~1900 e-rms
~3200 e-rms
High Gain
~450 e-
~900 e-
High Gain
~650 e-
~1300 e-
8 µW
15 µW
HG / LG
The chip can be operated up to 460Mrad and beyond
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Silicon Drift Detector
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Asic for SDD-based X-ray Spectrometers (G. De
Geronimo)
Gain 2.6 and
5.2V/fC
(0.83V/ke-)
5th order shaper
16 channels
(1700 x 200
µm2/ch)
2mW/channel
Analog and
leakage current
monitors
Temp sensor
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Asic for SDD-based X-ray Spectrometers (G. De
Geronimo)
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Asic for SDD-based X-ray Spectrometers (G. De
Geronimo)
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A New Dynamic Time over
Threshold Method
K. Shimazoe1, H. Takahashi1, T. Fujiwara2,
T. Furumiya3, J. Ohi3, Y. Kumazawa3
1Bioengineering, The University of Tokyo, Tokyo,Bunkyo-ku,
Japan
2Nuclear Engineering and Management, The University of
Tokyo, Tokyo,Bunkyo-ku, Japan
3Shimadzu Corporation, Kyoto, Japan
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A New Dynamic Time Over Threshold Method
(K. Shimazoe)
• Time Over Threshold (TOT) system has advantage over
pulse height measurements on its high integrity and low
power dissipation because of its binary readout and
circuit simplicity. However the relation between TOT and
input charge is strongly nonlinear and dynamic range is
limited. We propose a new dynamic TOT system which
converts the pulse height to pulse width with a
dynamically changing threshold. This kind of TOT
system can enable wider dynamic range and improves
linearity since the threshold follows the input signal and
even shorten the width of TOT pulse. We show the
concept of dynamic TOT system and results with
discrete circuits. It can improve the dynamic range and
theoretically it is possible to desired relation between
TOT and input charge by using dedicated threshold
function. We also designed and fabricated 48 channel
dynamic TOT ASIC with 0.25um TSMC CMOS technology.
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6
5
Voltage (V)
4
3
2
Wave1
Wave2
Wave3
Dynamic Threshold
1
0
0
5
10
15
20
25
30
35
40
45
50
Time (s)
1.4
1.2
Voltage (V)
1
0.8
0.6
0.4
Comp1_ftot
Comp2_ftot
Comp3_ftot
0.2
0
0
5
10
15
20
25
30
35
40
45
50
Time (s)
1.4
1.2
Voltage (V)
1
0.8
0.6
0.4
Comp1_dtot
Comp2_dtot
Comp3_dtot
0.2
0
0
5
10
15
20
25
30
35
40
45
50
Time (s)
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A New Dynamic Time Over Threshold Method
(K. Shimazoe)
CF
Shaper
DISC
-Av
Idet
Monostable
multivibrator
Cdet
R1
R2
V
CI
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3D interconnects
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Vertically Integrated Circuits at Fermilab (G.
Deptuch)
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Vertically Integrated Circuits at Fermilab (G.
Deptuch)
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3D integrated circuits
• Benefits
– Density
– Optimized processing (specialized layers e.g. analog/digital)
– Speed (reducing interconnects distance)
• Challenges
– Bonding (need high yields to be competitive)
– Packaging (thin wafers)
• Main customers
– Stacked microprocessors and SRAM devices
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3D integrated circuits (vendors)
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Tezzaron
MIT Lincoln
Labs
Ziptronix
W2W, C2W
W2W
W2W, C2W
Bonding
Cu-Cu
Conventional
oxide bonding
DBITM
tecnology.
Oxide bond
Via process
Via First
Via Last
Via
4um pitch,
1.2um diam,
6um deep
1.2um diam,
6um pitch
Process
Chartered
130nm CMOS
0.18um SOI
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Vertically Integrated Circuits at Fermilab (G.
Deptuch)
VIP1/VIP2
chips.
(Vertically
integrated pixel)
3 tiers: Data
sparsification,
Time stamp,
Analog
Time stamping
pixel readout
chip for ILC
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Vertically Integrated Circuits at Fermilab (G.
Deptuch)
VIPIC CHIP
Sensors fabricated at BNL; DBI (Vertically integrated
bonding done at Ziptronix (all in photon imaging
chip) (Light Sources)
process)
How it works:
X-ray Photon
Correlation
Spectroscopy (XPCS)
is a technique that is
used at X-ray light
sources to generate
speckle patterns for
the study of the
dynamics in various
equilibrium and nonequilibrium processes
The chip is divided in
16 group of 256 pixels
read out in parallel but
through separate
LVDS serial ports
Data sparsification is
performed in each
group
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New techniques in SOI pixel detectors (Y. Arai)
0.2um Silicon on
insulator CMOS
technology.
Slide: Y. Arai (Oct. 15, 2009@CLIC09)
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New techniques in SOI pixel detectors (Y. Arai)
Slide: Y. Arai (Oct. 15, 2009@CLIC09)
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Ultra Thin, Fully depleted MAPS based on
3D integration of Heterogeneous CMOS
layers (Wojciech Dulinski, Strasbourg)
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Ultra Thin, Fully depleted MAPS based on 3D integration of
Heterogeneous CMOS layers (Wojciech Dulinski)
• Aim: Fast, High precision radiation tolerant and
ultrathin CMOS sensors
• Solution: MAPS on fully depleted epitaxial
substrate with first stage buffer amplifier on the
same wafer and 3D coupling to the readout
electronics
• Requirements:
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Fast readout frame ~10us
Pixel pitch ~20um
Ultrathin ~50-100um
5uW/pixel, ENC ~12 e- rms, Gain ~150uV/eNSS-MIC conference, Orlando (October 2009)
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Ultra Thin, Fully depleted MAPS based on 3D integration of
Heterogeneous CMOS layers (Wojciech Dulinski)
NSS: XFAB
0.35um
Slide : W. Dulinski EUDET-JRA1 Meeting, Strasbourg, March 2009
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SiPM
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SiPM principle
A SiPM is a matrix of Single Photon
Avalanche Diodes (SPADs) with a
common output. A SPAD is build as
a PIPN junction diode in series with
a quench resistance. It is biased
over the breakdown voltage.
i(t)
90mA
60mA
30mA
François Powolny
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The output of
the SiPM is
the sum of all
the SPADs
t
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SiPM
François Powolny
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SPIROC ASIC (Wei Shen)
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SPIROC ASIC (Wei Shen)
1MIP~16 pixels fired
Threshold ½ MIP
Jitter<500ps
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SPIROC ASIC (Wei Shen)
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BASIC chip (C. Marzocca)
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BASIC chip (C. Marzocca)
Fast Path: fast
trigger signal
Slow
Path:
energy
Low impedance, High dinamic range,
flexibility in processing the current
Rin=17Ohm
Chip in 0.35mm
BW=250MHz
3.3V, 6.6mW/channel
(190mmx590mm)
SiPM bias fine tunning
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Readout of SiPM for TOF PET
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Readout of SiPM for TOF PET
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Readout of SiPM for TOF PET
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Summary
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Summary
• Some ASICs that were presented at NSS have
been presented in this presentation.
• An international collaboration in the field of 3D
IC for HEP was created. 3D IC brings benefits
and challenges and seems a direction industry
is taking.
• SiPMs are emerging as candidates to replace
Photomultiplier tubes, specially in medical
imaging due to insensitivity to magnetic fields
and operating « low voltage ». They were
chosen in HEP for the Hadron Calorimeter for
the ILC.
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Other designs of interest (for completeness)
• A Pixel Front-End ASIC in 0.13 μm CMOS for the NA62
Experiment with on Pixel 100ps Time-to-Digital
Conversion
• FE-I4: the New ATLAS Pixel Chip for Upgraded LHC
Luminosities
• PARISROC, a Photomultiplier Array Integrated Read Out
Chip
• FREDA: a Programmable Mixed Signal ASIC for Gas
Micro-Strip Detectors Having a Wide Range of Input
Capacitance
• Design and Performance of the ABCN-25 Readout Chip
for the ATLAS Inner Detector Upgrade
• Low Noise 64-Channel ASIC for Si, GaAs and CdTe Strip
Detectors
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Additional Slides
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Medipix3 Dicing options
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X [µm]
Y [µm]
Active
Area
Medipix2 and Timepix
14111
16120
87.1%
Medipix3 top and
bottom WB
14100
17300
81.2%
Medipix3 bottom WB
14100
15900
88.4%
Medipix3 top and
bottom TVS
14100
15300
91.9%
Medipix3 bottom TVS
14100
14900
94.3%
mmmm
mm
15.9
14.9
15.3
17.3
Multiple dicing options
14.1 mm
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Equalization procedure
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Matrix equalization
Equalized
8000
250
Not Equalized
7000
r.m.s=2.8 DAC
steps
r.m.s=38 DAC
steps
5000
150
4000
100
3000
Number of Pixels
Number of Pixels
6000
200
2000
50
1000
0
0
50
100
150
200
250
0
300
Threshold (DAC steps)
1 DAC step ~ 45e- (to be measured with sources)
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Chip power consumption
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Chip Power Consumption
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SPIROC
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SPIROC
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Electrical model for the SiPM
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Vertically Integrated Circuits at Fermilab (G.
Deptuch)
VIPIC CHIP
(Vertically integrated
photon imaging
chip)
How it works:
X-ray Photon
Correlation
Spectroscopy (XPCS)
is a technique that is
used at X-ray light
sources to generate
speckle patterns for
the study of the
dynamics in various
equilibrium and nonequilibrium processes
The chip is divided in
16 group of 256 pixels
read out in parallel but
through separate
LVDS serial ports
Data sparsification is
performed in each
group
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Preamplifier output in the MPIX3 chip
0.35
0.3
Voltage [V]
0.25
0.2
0.15
0.1
0.05
0
-0.05
-2.00E-07
0.3
y = 0.0092x + 0.0097
0.25
0.2
0.15
0.1
0.05
0
8.00E-07
1.80E-06
2.80E-06
Time [s]
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Preamplifier Output Amplitude [V]
0.35
Pream_10D
Pream_20D
Pream_40D
Pream_60D
Pream_80D
Pream_100D
Pream_120D
Pream_140D
3.80E-06
4.80E-06
0
5
10
15
20
25
30
35
Input Charge [ke-]
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Stud Bonding
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Stud bonding (http://www.flipchips.com/tutorial03.html)
• The gold stud bump flip chip assembly process
creates conductive gold bumps on the die bond
pads, and connects the die to the circuit board
or substrate with adhesive or ultrasonic
assembly. Stud bumping requires no underbump metallization (UBM), and thus does not
require wafer processing; individual die can be
stud bumped as easily as they can be wire
bonded.
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Stud bonding (http://www.flipchips.com/tutorial03.html)
•
•
•
•
•
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ADVANTAGES AND LIMITATIONS
Gold stud bump flip chip offers several advantages. The bumping
equipment, a wire bonder or dedicated stud bumper, is widely available
and well characterized. Since stud bumps are formed by wire bonders,
they can be placed anywhere a wire bond might be placed. They can
easily achieve pitches of less than 100 microns and be placed on pads
of less than 75 microns.
Since stud bumping can be done on a wire bonder, it does not require
wafers or under-bump metallization (UBM). Single, off-the-shelf die can
be bumped and flipped without pre-processing. This makes stud bump
flip chip fast, efficient, and flexible for product development,
prototyping and low to medium volume production, while easy to scale
up to high volume wafer-based production with automated equipment.
Because stud bumping is a serial process, the bumping time required
increases with the number of bumps. However, high speed equipment
now can place as many as 12 bumps per second. Stud bump
assemblies demand more precise die placement equipment and are
less tolerant of placement errors than self-aligning solder assemblies.
Each of the stud bump assembly processes has advantages and
limitations that suit it for specific applications. Stud bump assembly
has been successful in a wide range of applications. Selecting the most
appropriate assembly process depends on the application, the die size
and number of bumps, the substrate, equipment availability, cost, and
other considerations. Choosing the proper process is the best
assurance of success.
NSS-MIC conference, Orlando (October 2009)
R. Ballabriga
Pile-up rejector block (de Geronimo)
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NSS-MIC conference, Orlando (October 2009)
R. Ballabriga
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NSS-MIC conference, Orlando (October 2009)
R. Ballabriga