Transcript L11a_4345_Sp02

The Nanofab Group
EE 4345 – Semiconductor Electronics
Design Project – Spring 2002
Kevin Bradford
Corey Clark
Carlos Garcia
Guillaume Gbetibouo
Eric Goebel
Fariba Pouya
Technical Project 1.5
ANALOG BiCMOS
Introduction
What is BiCMOS?
BiCMOS technology combines
Bipolar and CMOS transistors onto a
single integrated circuit where the
advantages of both can be utilized.
Advantages of CMOS over Bipolar
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Power dissipation
Noise margin
Packing density
The ability to integrate large comples
functions with high yields
Advantages of Bipolar over CMOS
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Switching speed
Currents drive per unit area
Noise perfomance
Analog capability
Input/output speed
Advantages of BiCMOS Technology
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Improved speed over CMOS
Lower power dissipation than Bipolar
Flexible input/outputs
High performance analog
Latch up immunity
Analog BiCMOS Complexity
Analog BiCMOS processes are characterized by their
complexity, most needing15 masks. Some up to 30 masks.
Advantages of complexity
• Higher performance
analog circuits
• Reduced design efforts
• Faster design cycles
Disadvantages of complexity
• Higher wafer cost
• Longer manufacturing
time
• Lower process yields
Evolution of BiCMOS from CMOS
BiCMOS technologies have tended to evolve from CMOS
processes in order to obtain the highest CMOS
performance possible.
The bipolar processing steps have been added to the core
CMOS flow to realize the desired device characteristics.
Fabrication Equipment
Molecular Beam Epitaxy
(MBE)
Fabrication Equipment
Photoresist Spinner
Bake-out Ovens
Fabrication Equipment
Mask Aligner
Reactive Ion Etching (RIE)
Fabrication Equipment
Chemical Vapor Deposition
(CVD)
Plasma Quest Sputter
Fabrication Equipment
Plasma Sputter
Perkin-Elmer MBE
Fabrication Equipment
Probe Station
Scanning Electron
Microscope (SEM)
N-well CMOS Structure
• NMOS device, built in a 15um thick P-epitaxial layer on top
of
P+substrate
•PMOS transistor, built in an implanted N-well approximately 5um deep
•P+ substrate is used to reduce latch up susceptibility by providing a low
impedance patch through a vertical PNP device
•Polysilicon gates are used for both the PMOS and NMOS transistors
Adding NPN Bipolar Transistor
The simplest way to add an NPN bipolar transistor to the previous CMOS
structure is by using PMOS N-well as the collector of the Bipolar device
and introducing an additional mask level for the P-base region.
• the P-base is approx 1 um deep with a doping level of about 1e17 atoms/cm^3
• the N+ source/drain ion implantation step is used for the emitter and
collector contact of the bipolar structure
• the P+ source/drain ion implantation step is used to create a P+ base
contact to minimize the base series resistance
Contacts
Contacts
metal
n-type s/c
qcs
qfm
qfBn
qVbi
qfs,n
EFm
Depl reg
qf’n
Ec
EFn
EFi
Ev
Pattern Shift – NBL Shadow (1/2)
Pattern Shift – NBL Shadow (2/2)
Stacking faults
Other Causes
• An extra plane of atoms
• Temprature
•The lack of a plane of atoms
•Pressure
•Wafer pre-leaning
•Growth precursor
P Isolation vs. CDI
P Isolation
Collector Diffused Isolation
BiCMOS Isolation Consideration
• Key factor in determining overall circuit performance and
density
• Collector Diffused Isolation (CDI)
– N-well used to form collector of NPN transistor
– Base and emitter consist of successive counterdoping of
the well.
– CDI transistors
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Saturate prematurely
Limits low-voltage operation
Complicates device modeling
Causes undesired substrate injection
Applications of BiCMOS Technology
• System-on-a-Chip Technology
– personal Internet access devices
– set-top boxes
– thin clients
References
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Carter, Ronald. “Lecture 9 – EE 5342” UTA
Cheung, Nathan “ Lecture 17 – EE 143” UC Berkeley
http: //et.nmso.edu/ETCLASSES/vlsi/files/CRYSTAL.HTM
Hastings, Alan “The Art of Analog Layout”, Prentice Hall, New Jersey,
2001
• Campbell, Stephen A. , “The Science and Engineering of
Microelectronic Fabrication”, Oxford University Press, New York,
2001
• Alvarez, Antonio, “BiCMOS Technology and Applications”, Prentice
Hall, New Jersey, 2001