Transcript Fault tolerant transformation - Université de Bretagne Occidentale

Building Cad Prototyping Tool for
Emerging Nanoscale Fabrics
Catherine Dezan ([email protected])
Joined work between
Lester(France) and
UMASS(USA)
Contributors:
Université de Bretagne
Occidentale(LESTER,
CNRS)
Catherine Dezan
Loic Lagadec
European Nano Systems Conference, 12/03/2007
University of Massachusetts
at Amherst
Michael Leuchtenburg,
Teng Wang,
Pritish Narayanan,
Andras Moritz
Motivation
 Bottom-up strategies -> more defective
(10-9 to 10-7 failure rate in CMOS technology,
10-2to 10-1 failure rate in emerging
nanotechnologies)
-> CAD tool should take this into account
 Evolutive nanofabrics (Semiconductor
Nanowire -> Carbone Nanotube) needs
generic CAD tool for a quick adaptation
European Nano Systems Conference, 12/03/2007
Outline of the talk
 Defective Hybrid Nanofabrics
 Proposal of prototyping tool based on Nanofabric
specification
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
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
Design flow
Models for Nanofabric Specification
Transformations based on Nanofabric models
Fault-tolerant transformations
 Conclusion
European Nano Systems Conference, 12/03/2007
Emerging Nanofabrics
Our references to nanofabrics, based on progress of
Semiconductor Nanowire manufacturing [Lieber2007]
are hybrid CMOS/Nano fabrics:
NASIC[Moritz 2004],
NanoPla[Dehon2005],
CMOL[Likharev2005], FPNI[Snider2007]
(a)
(c)
(b)
(d)
Possible manufacturing procedures
(demonstrated for every step, but
not yet the whole process)
European Nano Systems Conference, 12/03/2007
Existing CAD tools are specific
 These nanofabrics propose a range of test
applications on their nano support
Ex: microprocessor (NASIC), Neuromorphic
networks(CMOL), general purpose
 Each specific fabric proposes its specific
CAD tools:
Ex:CMOL FPGA compiler, FPNI compiler,
NanoPla CAD
European Nano Systems Conference, 12/03/2007
Towards a generic prototyping
CAD tool
Main features:
 Generic CAD tool: not specific CAD tool adapted
to a single Nanofabric
 Based on Nanofabric Specification through models
 Design flow from behavioral description towards
symbolic layout
 Fault-tolerant transformations
European Nano Systems Conference, 12/03/2007
European Nano Systems Conference, 12/03/2007
Nanofabrics Specification
through models
Abstractions of some nanofabric mechanism
Computational
model
Technological
model
European Nano Systems Conference, 12/03/2007
Architectural
model
Fault model
Computational and
Architectural models
Workshare between
• nano
Interconnect(FPNI),
Interconnect +computation
(NanoPla,CMOL,NASIC)
and its organization(2 or
multi-level logic)
• CMOS
I/O, specific gate(inv),
control
European Nano Systems Conference, 12/03/2007
Structural and
hierarchical organization
of building components
in tiles
Technological and Fault models
Physical constraints for
place-and-route
routines:
- doping constraints
(NASIC)
- Connection constraints
for reconfigurable
fabric
- Defect map
European Nano Systems Conference, 12/03/2007
Fault types with distribution
(uniform/cluster) and rates:
•permanent defects(manufacturing
process), stuck-on,stuck-off
transistor, broken nanowire
•Transient faults (internal noise,
particle impact, ..)
•Process variation(channel length,
doping, wire thickness)
(1)
(2)
(3)
European Nano Systems Conference, 12/03/2007
Behavioral transformations(1)
In addition to classical high-level transformations, we
take into account:
 pre-partionning for Nano/CMOS transformation
(according to the computational model)
 fault-tolerant transformations(adding voting spec,
Error correcting codes, transfert in CMOS)
(according to fault model)
European Nano Systems Conference, 12/03/2007
Case study of NASIC fabric(1)
Computational
model: CMOS
limited for
control signal,
computation
4bits -> 7bits
with 2 level
with BCH(7,4,1)
logic
Fault model:
Rebuild
permanent,
computation
transient,
DAG
uniform/cluster
European Nano Systems Conference, 12/03/2007
Fault-tolerant
transformation:
Data encoded in
BCH codes in
order to build
redundant logic
(Hamming distance
related to fault rate)
Synthesis and structural
transformations(2)
 Synthesis with an external tool (SIS,ABC) directives are
produced by the computational model and architectural
model (ex: 2 level logic -> pla synthesis)
 Structural transformations to add specific circuitry
(decodeur for I/O, signal restoration , additional CMOS
circuitry..) related to the architectural model
 Fault-tolerant transformations based on the structural
representation of the application: structural copies defined at
fine grain or coarse grain( using voters- in CMOS) related to
fault model
European Nano Systems Conference, 12/03/2007
Example of fault-tolerant
transformations at structural level (2)
Architectural model:
2D grid with FET,
microwires around
tiles
and’
and
or
External tool for
logic synthesis
(SIS, ABC)
S=f(x,y,z)
x
y
z
s
pla
or’
European Nano Systems Conference, 12/03/2007
Fault tolerant
transformation:
structural
redundancy at
fine grain
Yield projection(2)
Fault-tolerant
techniques produce
different yield
related to fault rate,
types of fault and
distribution
-> need of
iterations in flow
design
European Nano Systems Conference, 12/03/2007
Integration of the yield
simulator for NASIC
Physical design (3)
Transformations at this level include partitioning, placement
and routing onto the nanofabric:
 Reconfigurable fabrics have congestion problem for placeand-route due to the restriction of connections(adaptation of
pathfinder algorithm is appropriate - feasibility proved with
our previous experiment on FPGA CAD tool)
 Generic heuristics like simulated annealing, clustering may
be suitable for placement into tiles and between tiles
-> custom adaptation is made using the technological model
Possibility to add new custom routines to achieve better results
European Nano Systems Conference, 12/03/2007
Symbolic layout for NASIC(3)
Technological
model: Doping
constraints
Program Counter
+ Rom + decoder
European Nano Systems Conference, 12/03/2007
Place-and-route
routines with
fixed size of tiles
Register file + Alu
Conclusion
 Proposal of a generic tool based on
Nanofabric Specification
 Proposal of adequate models correlated to
transformations
 One instance based on NASIC fabric was
developped
European Nano Systems Conference, 12/03/2007
Future investigations
 Investigating on more detailed models and their
automatic integration in the generic framework
 Adding more fault-tolerant transformations and
hybrid fabric related transformations
(probabilistic computation and synthesis?)
 More case studies to consolidate and validate the
framework
[email protected]
European Nano Systems Conference, 12/03/2007
Thanks
[email protected]
European Nano Systems Conference, 12/03/2007