Transcript Venkata
Prospects for Terabit-scale nano electronic memories Venkata R.Malladi Instructor : Dr.Damian Introduction • • • • • • Motivation What are Nano electronic memories? CMOS vs. NANO What is that it got to do with terabit-scale? What are hybrid memories? Is the present day architecture needed to be totally replaced for Nano scaled devices? • Results Motivation • • • • CMOS Memory “Complementary Metal Oxide Semiconductor” Traditional memory architecture Chipmakers won’t be able to shrink transistors much longer to fit more on a chip • Need new ways to make memory chips more powerful and less expensive • Solution: Nano-Scale Electronic Memories. Nano-Scale Electronics • Technology that manipulates physical structures at the molecular scale • Can we, by moving to molecular scale electronics, buy a little bit more shrinkage? • Is is possible? Is it economical? • Example: nanowires Nanowires • Currently wires are made out of silicon and other materials that are ~ 15nm in diameter • These are itsy bitsy wires enabling high density • They have high resistance; hence limited speed • Nanowires are only a few atoms wide; have been fabricated in many labs • Two crossing nanowires form a switch; the switch is created only from a few molecules. Nano Electronic memories • Nano electronics is the technology where it pairs traditional silicon chips with manipulation of molecules themselves • Advantages Greater density Lower power consumption High speed • Field effect transistors with nanotube or nanowire conducting channels, as well as quantum dot-based single electron transistors, might serve in a limited capacity to enhance the performance of CMOS chips in a hybrid nano/microelectronic architecture • Application : Toshiba Announces Availability of 32-Bit RISC Microcontroller with 2 Megabytes of Embedded NANO FLASH(TM) Memory CMOS Vs NANO • CMOS (Top –down Fabrication) Nano (Bottom-up fabrication) Eg : Lithography Eg : Self fabrication Limited resolution Molecular resolution Expensive & Arbitrary structures Potentially cheap & Regular structures Reliable Higher defect rates Nano-Scale Circuits - Advantages • Greater density • Lower power consumption • Higher speed Nano-Scale Circuits - Disadvantages • High defect rates is Due to number of bad nano devices • The number of bad devices is around ~15% and it has to be reduced to ~2% to get and advantage in density. • In order to achieve that we use • 1. Repair most technique with hamming error code correction(Execution time scaling linearly with number of bits) • 2. Exhaustive Search approach(exponentially large execution time) Prospects for Terascale (240) • Prospects for Terabit-scale nano memories? Having Memory array configuration (Bad bit exclusion) using the following techniques: Most repair techniques complemented with ECC (Error Correction Codes) Using hybrid semiconductor/nano device circuits Hybrid memories Hybrid Memories • Hybrid memories combine the advantages of Nano-scale components and reliability of CMOS circuits • Hybrid memories use single-molecule single transistor in place of present day CMOS circuits • The architectural challenges of Hybrid memories Bad bit Nano devices Limitation due to integration technique Vulnerability due to Random charged effects • Approach to address the above problem Use Memory reconfiguration Results • The speed and Power and memory density if going to be the main advantages of Nano electronics. • Potential development in future using Nano devices Progress of technologies Capacity of magnetic hard disks:• 1980’s: 30% growth per year•early 1990’s: 60% growth per year•late 1990’s: 130% growth per year•disk capacity doubling every 9 months(twice the pace of Moore’s Law) • Queries ?