Transcript CMOS_INVERTER CHARACTERIZATION

CIRCUIT CHARACTERIZATION
AND PERFORMANCE
ESTIMATION CONTD……
Prof. N.S.Murthy,
PPKKP/UNIMAP
[email protected]
4/13/2016
EMT251_NSM_09
1
The CMOS Inverter: A First
Glance
V
DD
V in
V out
CL
CMOS Inverter
N Well
VDD
VDD
PMOS
2l
Contacts
PMOS
In
Out
In
Out
Metal 1
Polysilicon
NMOS
NMOS
GND
Two Inverters
Share power and ground
Abut cells
VDD
Connect in Metal
CMOS Inverter
First-Order DC Analysis
V DD
V DD
Rp
V out
V out
Rn
V in 5 V DD
V in 5 0
VOL = 0
VOH = VDD
VM = f(Rn, Rp)
CMOS Inverter Load Characteristics
ID n
PMOS
Vin = 0
Vin = 2.5
Vin = 0.5
Vin = 2
Vin = 1
Vin = 1.5
Vin = 1.5
Vin = 1
Vin = 1.5
Vin = 2
Vin = 2.5
NMOS
Vin = 1
Vin = 0.5
Vin = 0
Vout
CMOS Inverter VTC
NMOS off
PMOS res
2.5
Vout
2
NMOS s at
PMOS res
1
1.5
NMOS sat
PMOS sat
0.5
NMOS res
PMOS sat
0.5
1
1.5
2
NMOS res
PMOS off
2.5
Vin
Determining VIH and VIL
Vout
V OH
VM
V in
V OL
V IL
V IH
A simplified approach
Gain as a function of VDD
2.5
0.2
2
0.15
Vout(V)
Vout (V)
1.5
0.1
1
0.05
0.5
Gain=-1
0
0
0.5
1.5
1
V (V)
in
2
2.5
0
0
0.05
0.1
V (V)
in
0.15
0.2
Simulated VTC
2.5
2
Vout(V)
1.5
1
0.5
0
0
0.5
1
1.5
V (V)
in
2
2.5
Impact of Process Variations
2.5
2
Good PMOS
Bad NMOS
Vout(V)
1.5
Nominal
1
Good NMOS
Bad PMOS
0.5
0
0
0.5
1
1.5
Vin (V)
2
2.5
Propagation
Delay
CMOS Inverter Propagation Delay
VDD
tpHL = f(R on.CL)
= 0.69 RonCL
Vout
ln(0.5)
Vout
CL
Ron
1
VDD
0.5
0.36
Vin = V DD
RonCL
t
CMOS Inverters
VDD
PMOS
1.2mm
=2l
In
Out
Metal1
Polysilicon
NMOS
GND
Transient Response
3
2.5
?
Vout(V)
2
tp = 0.69 CL (Reqn+Reqp)/2
1.5
1
tpHL
tpLH
0.5
0
-0.5
0
0.5
1
1.5
t (sec)
2
2.5
-10
x 10
Design for Performance
• Keep capacitances small
• Increase transistor sizes
– watch out for self-loading!
• Increase VDD (????)
Delay as a function of VDD
5.5
5
tp(normalized)
4.5
4
3.5
3
2.5
2
1.5
1
0.8
1
1.2
1.4
1.6
V
1.8
(V)
DD
2
2.2
2.4
Device Sizing
-11
3.8
x 10
(for fixed load)
3.6
3.4
tp(sec)
3.2
3
2.8
Self-loading effect:
Intrinsic capacitances
dominate
2.6
2.4
2.2
2
2
4
6
8
S
10
12
14
NMOS/PMOS ratio
-11
5
x 10
tpHL
tpLH
tp(sec)
4.5
b = Wp/Wn
tp
4
3.5
3
1
1.5
2
2.5
3
b
3.5
4
4.5
5
Inverter
Sizing
Inverter Chain
In
Out
CL
If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?
May need some additional constraints.
Inverter Delay
• Minimum length devices, L=0.25mm
• Assume that for WP = 2WN =2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
• Analyze as an RC network
 WP 

RP  Runit 
 Wunit 
1
 WN 

 Runit 
 Wunit 
Delay (D): tpHL = (ln 2) RNCL
Load for the next stage:
1
 RN  RW
tpLH = (ln 2) RPCL
W
C gin  3
Cunit
Wunit
2W
W
Inverter with Load
Delay
RW
CL
RW
Load (CL)
tp = k RWCL
k is a constant, equal to 0.69
Assumptions: no load -> zero delay
Wunit = 1
Inverter with Load
CP = 2Cunit
Delay
2W
W
CN = Cunit
Cint
CL
Load
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)
= Delay (Internal) + Delay (Load)
Example
In
C1
Out
1
f
f2
CL= 8 C1
CL/C1 has to be evenly distributed across N = 3 stages:
f 38 2
Optimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
N
CL  F  Cin  f Cin with N 
ln f
Buffer Design
1
f
tp
1
64
65
2
8
18
64
3
4
15
64
4
2.8
15.3
64
1
8
1
4
16
2.8
8
1
N
64
22.6
Power
Dissipation
Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors
Dynamic Power Dissipation
Vdd
Vin
Vout
CL
2
dd
L
Energy/transition = C * V
L
Power = Energy/transition * f = C * V
2
dd
*f
Not a function of Ltransistor
sizes!
dd
Need to reduce C , V , and f to reduce power.
Modification for Circuits with Reduced Swing
Vdd
Vdd
Vdd -Vt
CL
E 0  1 = CL  Vdd   Vdd – Vt 
Can exploit reduced sw ing to low er power
(e.g., reduced bit-line swing in memory)
Short Circuit Currents
Vd d
Vin
Vout
CL
IVDD (mA)
0.15
0.10
0.05
0.0
1.0
2.0
3.0
Vin (V)
4.0
5.0
How to keep Short-Circuit Currents Low?
Short circuit current goes to zero if tfall >> trise,
but can’t do this for cascade logic, so ...
Minimizing Short-Circuit Power
8
7
6
Vdd =3.3
Pnorm
5
4
Vdd =2.5
3
2
1
Vdd =1.5
0
0
1
2
3
t /t
sin sout
4
5
Leakage
Vd d
Vout
Drain Junction
Leakage
Sub-Threshold
Current
Sub-threshold current one of most compelling issues
Sub-Threshold
in low-energy
circuitCurrent
design!Dominant Factor
Reverse-Biased Diode Leakage
GATE
p+
p+
N
Reverse Leakage Current
+
V
- dd
IDL = JS  A
2
JS = JS
1-5pA/
for a 1.2
technology
= 10-100
at 25
degCMOS
C for 0.25mm
CMOS
mmpA/mm2
mm
JS doubles for every 9 deg C!
Js double with every 9oC increase in temperature
Subthreshold Leakage Component
Static Power Consumption
Vd d
Istat
Vout
Vin =5V
CL
Pstat = P(In=1).Vdd . Istat
Wasted •energy
… over dynamic consumption
Dominates
Should be avoided in almost all cases,
• Not a function of switching frequency
but could help reducing energy in others (e.g. sense amps)
Principles for Power Reduction
• Prime choice: Reduce voltage!
– Recent years have seen an acceleration in
supply voltage reduction
– Design at very low voltages still open
question (0.6 … 0.9 V by 2010!)
• Reduce switching activity
• Reduce physical capacitance
– Device Sizing: for F=20
• fopt(energy)=3.53, fopt(performance)=4.47
Impact of
Technology
Scaling
Goals of Technology Scaling
• Make things cheaper:
– Want to sell more functions (transistors) per
chip for the same money
– Build same products cheaper, sell the same
part for less money
– Price of a transistor has to be reduced
• But also want to be faster, smaller, lower
power
Technology Scaling
• Goals of scaling the dimensions by 30%:
– Reduce gate delay by 30% (increase operating
frequency by 43%)
– Double transistor density
– Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency
• Die size used to increase by 14% per generation
• Technology generation spans 2-3 years
Technology Evolution (2000 data)
International Technology Roadmap for Semiconductors
Year of
Introduction
1999
Technology node
[nm]
180
Supply [V]
2000
2001
2004
2008
2011
2014
130
90
60
40
30
0.6-0.9
0.5-0.6
0.3-0.6
8
9
9-10
10
3.5-2
7.1-2.5
11-3
14.9
-3.6
1.5-1.8 1.5-1.8 1.2-1.5 0.9-1.2
Wiring levels
6-7
6-7
7
Max frequency
[GHz],Local-Global
1.2
Max mP power [W]
90
106
130
160
171
177
186
Bat. power [W]
1.4
1.7
2.0
2.4
2.1
2.3
2.5
1.6-1.4 2.1-1.6
Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm
Technology Evolution (1999)
Technology Scaling (1)
Minimum Feature Size (micron)
10
10
10
10
2
1
0
-1
-2
10
1960
1970
1980
1990
2000
Year
Minimum Feature Size
2010
Technology Scaling (3)
tp decreases by 13%/year
50% every 5 years!
Propagation Delay
Technology Scaling (4)
/
4
x
3
1
0.1
0.01
80
MPU
DSP
85
90
Year
(a) Power dissipation vs. year.
95
1000

3
10
ars
e
y
0.7

100

Power Dissipation (W)
100
rs
Power Density (mW/mm2 )
ea
x 1.4 / 3 y
10
1
1
Scaling Factor 
（normalized by 4 mm design rule ）
(b) Power density vs. scaling factor.
From Kuroda
10
Technology Scaling Models
• Full Scaling (Constant Electrical Field)
ideal model — dimensions and voltage scale
together by the same factor S
• Fixed Voltage Scaling
most common model until recently —
only dimensions scale, voltages remain constant
• General Scaling
most realistic for todays situation —
voltages and dimensions scale with different factors
Scaling Relationships for Long Channel
Devices
mProcessor Scaling
P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001
mProcessor Power
P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001
mProcessor Performance
P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001
2010 Outlook
• Performance 2X/16 months
– 1 TIP (terra instructions/s)
– 30 GHz clock
• Size
– No of transistors: 2 Billion
– Die: 40*40 mm
• Power
– 10kW!!
– Leakage: 1/3 active Power
P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001
Some interesting questions
• What will cause this model to break?
• When will it break?
• Will the model gradually slow down?
– Power and power density
– Leakage
– Process Variation