Transcript +V - EnhanceEdu

THE INVERTER
DYNAMICS
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
Inverter Dynamics
 Dynamic Behavior
 Delay Definitions
 Voltage Transfer Characteristic
 Switching Threshold
 Propagation Delay
 Transient Response
 Inverter Sizing
 Power Dissipation
 Short Circuit Currents
 Technology Scaling
Dynamic Behavior
Propagation Delay, Tp
•Defines how quickly output is affected by input
•Measured between 50% transition from input to output
•tpLH defines delay for output going from low to high
•tpHL defines delay for output going from high to low
•Overall delay, tp, defined as the average of tpLH and tpHL
Dynamic Behavior
Rise and fall time, Tr and Tf
•Defines slope of the signal
•Defined between the 10% and 90% of the signal
swing
Propagation delay and rise and fall times affected by
the fan-out due to larger capacitance loads
Delay Definitions
Vin
50%
t
Vout
t
pHL
t
pLH
90%
50%
10%
tf
t
tr
The Ring Oscillator
•A standard method is needed to measure the gate
delay
•It is based on the ring oscillator
•2Ntp >> tf + tr for proper operation
Ring Oscillator
v1
v0
v0
v2
v1
v3
v4
v5
T = 2  tp N
v5
Voltage Transfer
Characteristic
CMOS Inverter Load Characteristics
VDD
G
S
D
Vin
Vout
CL
D
G
S
PMOS Load Lines
VDD
IDn
G
V in = V DD +VGSp
IDn = - IDp
V out = VDD +VDSp
S
D
Vin
Vout
D
V out
CL
G
IDp
S
IDn
IDn
Vin=0
Vin=0
Vin=3
Vin=3
V DSp
V DSp
VGSp=-2
VGSp=-5
Vin = V DD+VGSp
IDn = - IDp
Vout = V DD+VDSp
Vout
CMOS Inverter Load Lines
PMOS
2.5
NMOS
X 10-4
Vin = 0V
2
Vin = 2.5V
Vin = 0.5V
1.5
Vin = 2.0V
1
Vin = 1.0V
Vin = 1V Vin = 1.5V
Vin = 0.5V
Vin = 2V
0.5
Vin = 1.5V
Vin = 2.0V
0
0
V = 2.5V
in
Vin = 1.5V
Vin = 1.0V
Vin = 0.5V
0.5
1
1.5
2
2.5
Vin = 0V
Vout (V)
0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V
CMOS Inverter VTC
NMOS off
PMOS res
2.5
2
1.5
1
0.5
0
NMOS sat
PMOS res
Vout (V)
NMOS sat
PMOS sat
NMOS res
PMOS sat
0
0.5
1
Vin
1.5
(V)
2
NMOS res
PMOS off
2.5
Cutoff
Linear
Saturation
pMOS
Vin -VDD= VGS> VT
Vin -VDD=VGS< VT
Vin -Vout=VGD< VT
Vin -VDD=VGS> VT
Vin -Vout=VGD>VT
nMOS
Vin = VGS< VT
Vin =VGS> VT
Vin -Vout =VGD> VT
Vin =VGS> VT
Vin -Vout =VGD< VT
VDD
Regions of operations
For nMOS and pMOS
In CMOS inverter
G
S
D
Vin
Vout
D
G
S
CL
CMOS Inverter Load Characteristics
•For valid dc operating points:
•current through NMOS = current through PMOS
•=> dc operating points are the intersection of load lines
•All operating points located at high or low output levels
•=> VTC has narrow transition zone
•high gain of transistors during switching
•transistors in saturation
•high transconductance (gm)
•high output resistance (voltage controlled current source)
Switching Threshold
• VM where Vin = Vout (both PMOS and NMOS in saturation
since VDS = VGS)
VM  rVDD/(1 + r) where r = kpVDSATp/knVDSATn
• Switching threshold set by the ratio r, which compares
the relative driving strengths of the PMOS and NMOS
transistors
• Want VM = VDD/2 (to have comparable high and low noise
margins), so want r  1
(W/L)p =kn’VDSATn(VM-VTn-VDSATn/2)
(W/L)n kp’VDSATp(VDD-VM+VTp+VDSATp/2)
Switch Threshold Example
• In 0.25 mm CMOS process, using
parameters from table, VDD = 2.5V, and
minimum size NMOS ((W/L)n of 1.5)
VT0(V)
(V0.5)
VDSAT(V)
k’(A/V2)
(V-1)
NMOS
0.43
0.4
0.63
115 x 10-6
0.06
PMOS
-0.4
-0.4
-1
-30 x 10-6
-0.1
(W/L)p 115 x 10-6 0.63 (1.25 – 0.43 – 0.63/2)
=
(W/L)n
x
-30 x
10-6
x
-1.0
(1.25 – 0.4 – 1.0/2)
(W/L)p = 3.5 x 1.5 = 5.25 for a VM of 1.25V
= 3.5
Simulated Inverter VM
1.5
1.4
VM is relatively insensitive to
variations in device ratio
 setting the ratio to 3, 2.5
and 2 gives VM’s of 1.22V,
1.18V, and 1.13V

1.3
1.2
1.1
1
Increasing the width of the
PMOS moves VM towards VDD

0.9
0.8
0 .1
1
(W/L)p/(W/L)n
Note: x-axis is semilog
~3.4
10
Noise Margins Determining VIH and
VIL
3
By definition, VIH and VIL are
where dVout/dVin = -1 (= gain)
VOH = VDD
2
VM
1
VOL = GND0
VIL
Vin VIH
A piece-wise linear
approximation of VTC
NMH = VDD - VIH
NML = VIL - GND
Approximating:
VIH = VM - VM /g
VIL = VM + (VDD - VM )/g
So high gain in the transition
region is very desirable
Vout (V)
CMOS Inverter VTC from Simulation
0.25um, (W/L)p/(W/L)n = 3.4
(W/L)n = 1.5 (min size)
VDD = 2.5V
2.5
2
1.5
1
0.5
0
VM  1.25V, g = -27.5
VIL = 1.2V, VIH = 1.3V
NML = NMH = 1.2
0
0.5
1
Vin (V)
1.5
2
2.5
(actual values are
VIL = 1.03V, VIH = 1.45V
NML = 1.03V & NMH = 1.05V)
Output resistance
low-output = 2.4k
high-output = 3.3k
Gain Determinates
Vin
0
0
-2
-4
-6
0.5
1
1.5
2
Gain is a function of the current slope
in the saturation region, for Vin = VM
(1+r)
g  ---------------------------------(VM-VTn-VDSATn/2)(n - p )
-8
-10
-12
-14
-16
-18
Determined by technology
parameters, especially .
Only designer influence through
supply voltage and VM (transistor
sizing).
Vout (V)
Impact of Process Variation
2.5
2
1.5
1
0.5
0
Good PMOS
Bad NMOS
Nominal
Bad PMOS
Good NMOS
Vin (V)
0
0.5
1
1.5
2
2.5
Pprocess variations (mostly) cause a shift in the switching
threshold
Scaling the Supply Voltage
2.5
0.2
Vout (V)
Vout (V)
2
1.5
0.15
0.1
1
0.05
0.5
Gain=-1
0
0
0
0
0.5
1
1.5
Vin (V)
2
Device threshold voltages are
kept (virtually) constant
2.5
0.05
0.1
0.15
0.2
Vin (V)
Device threshold voltages are
kept (virtually) constant
Propagation Delay
Switch Model of Dynamic Behavior
VDD
VDD
Rp
Vout
Vout
CL
CL
Rn
Vin = V DD
Vin = 0
 Gate response time is determined by the time to charge CL
through Rp (discharge CL through Rn)
What is the Inverter Driving?
VDD
VDD
M2
Vin
Cg4
Cdb2
Cgd12
M4
Vout
Cdb1
Cw
M1
Vout2
Cg3
M3
Interconnect
Fanout
Simplified
Model
Vin
Vout
CL
CMOS Inverter Propagation Delay
Approach 1
VDD
tpHL = CL Vswing/2
Iav
CL
Vout
~
Iav
Vin = V DD
CL
kn VDD
CMOS Inverter Propagation Delay
Approach 2
VDD
tpHL = f(R on.CL)
= 0.69 RonCL
Vout
ln(0.5)
Vout
CL
Ron
1
VDD
Vout  VOH e  t /( Ro nC L )
0.5
0.36
Vin = V DD
RonCL
t
CMOS Inverter: Transient Response
How can the designer build a fast gate?
•tpHL = f(Ron*CL)
•Keep output capacitance, CL, small
•low fan-out
•keep interconnections short (floor-plan your layout!)
•Decrease on-resistance of transistor
•increase W/L ratio
•make good contacts (slight effect)
MOS Transistor Small Signal Model
G
D
+
vgs
gmvgs
-
Define
S
ro
Determining VIH and VIL
VIH and VIL are based on derivative of VTC equal to -1
Transient Response
3
?
2.5
tp = 0.69 CL (Reqn+Reqp)/2
Vout(V)
2
1.5
tpLH
tpHL
1
0.5
0
-0.5
0
0.5
1
1.5
t (sec)
2
2.5
-10
x 10
Inverter Transient Response
3
VDD=2.5V
0.25mm
W/Ln = 1.5
W/Lp = 4.5
Reqn= 13 k ( 1.5)
Reqp= 31 k ( 4.5)
Vin
2.5
2
1.5
tpHL
1
tf
tpLH
tr
0.5
tpHL = 36 psec
0
tpLH = 29 psec
so
-0.5
0
0.5
1
1.5
t (sec)
2
2.5
x 10-10
From simulation: tpHL = 39.9 psec and
tp = 32.5 psec
tpLH = 31.7 psec
Delay as a function of VDD
5.5
5
tp(normalized)
4.5
4
3.5
3
2.5
2
1.5
1
0.8
1
1.2
1.4
1.6
V
1.8
(V)
DD
2
2.2
2.4
Sizing Impacts on Delay
x 10-11
3.8
for a fixed load
3.6
The majority of improvement is
obtained for S = 5.
3.4
3.2
Sizing factors larger than 10
barely yields any extra gain
(and cost significantly more
area).
3
2.8
2.6
2.4
2.2
2
1
3
5
7
9
S
11
13
15
self-loading effect
(intrinsic capacitance
dominates)
PMOS/NMOS Ratio Effects
5
x 10-11
tpLH
4.5
 of 2.4 (= 31 k/13 k)
gives symmetrical
response
tpHL
4
 of 1.6 to 1.9 gives
optimal performance
tp
3.5
3
1
2
3
 = (W/Lp)/(W/Ln)
4
5
Input Signal Rise/Fall Time
x 10-11
5.4
• The input signal changes gradually (and
both PMOS and NMOS conduct for a
brief time).
• This affects the current available for
charging/discharging CL and impacts
propagation delay.
5.2
5
4.8
4.6
4.4
4.2
4


tp increases linearly with increasing
input rise time, tr, once tr > tp
tr is due to the limited driving
capability of the preceding gate
3.8
3.6
0
2
4
6
ts(sec)
for a minimum-size inverter
with a fan-out of a single gate
8
x 10-11
Inverter Sizing
CMOS Inverter Sizing
Out
metal1
metal2
pdiff
In
metal1-poly via
polysilicon
VDD
PMOS (4/.24 = 16/1)
NMOS (2/.24 = 8/1)
metal1-diff via
ndiff
GND
metal2-metal1 via
Inverter Delay
• Minimum length devices, L=0.25mm
• Assume that for WP = 2WN =2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
• Analyze as an RC network
 WP 

RP  Runit 
 Wunit 
1
 WN 

 Runit 
 Wunit 
Delay (D): tpHL = (ln 2) RNCL
Load for the next stage:
1
 RN  RW
tpLH = (ln 2) RPCL
W
C gin  3
Cunit
Wunit
2W
W
Inverter with Load
Delay
RW
CL
RW
Load (CL)
tp = k RWCL
k is a constant, equal to 0.69
Assumptions: no load -> zero delay
Wunit = 1
Inverter with Load
CP = 2Cunit
Delay
2W
W
Cint
CL
CN = Cunit
Delay = kRW(Cint + CL) = kRW Cint(1+ CL /Cint)
= Delay (Internal) + Delay (Load)
Load
Delay Formula
t p  kR W C int (1 + C L / C int )  t p 0 (1 + f / 
Cint = Cgin
with   1
f = CL/Cgin
effective fanout
R = Runit/W ;
tp0 = 0.69RunitCunit
Cint =WCunit
)
Inverter Chain

Real goal is to minimize the delay through an inverter chain
In
Out
Cg,1
1
2
N
the delay of the j-th inverter stage is
tp,j = tp0 (1 + Cg,j+1/(Cg,j)) = tp0(1 + fj/ )
and
tp = tp1 + tp2 + . . . + tpN
so
tp = tp,j = tp0  (1 + Cg,j+1/(Cg,j))
• If CL is given
– How should the inverters be sized?
– How many stages are needed to minimize the delay?
CL
Optimum Delay and Number of
Stages
When each stage is sized by f and has same fanout f:
f N  F  CL / Cgin,1
Effective fanout of each stage:
f NF
Minimum path delay
(
t p  Nt p 0 1 + N F / 
)
Example
In
C1
Out
1
f
f2
CL= 8 C1
t p  3t p 0 (1 + 2 /  )
CL/C1 has to be evenly distributed across N = 3 stages:
f 38 2
Notice that in this case we may not have any time savings
Optimal Number of Inverters
• What is the optimal value for N given F (=fN) ?
– if the number of stages is too large, the intrinsic delay
dominates
– if the number of stages is too small, the effective fan-out
dominates


The optimum N is found by differentiating the minimum
delay divided by the number of stages and setting the
result to 0,
For  = 0 (ignoring self-loading) N = ln (F) and the
effective-fan out becomes f = e = 2.71828
Optimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
N
CL  F  Cin  f Cin with N 
ln f
t p 0 ln F  f


t p  Nt p 0 F /  + 1 
+
  ln f ln f
t p t p 0 ln F ln f  1   f


0
2
f

ln f
(
1/ N
)
For  = 0, f = e, N = lnF



f  exp (1 +  f )
Optimum Effective Fan-Out
5
7
6
4.5
5
4
4
3.5
3
2
3
1
2.5
0
0
0.5
1
1.5

2
2.5
3
1
1.5
2
2.5
3
3.5
4
4.5
f
• Choosing f larger than optimum has little effect on delay and reduces the
number of stages (and area).
– Common practice to use f = 4 (for  = 1)
– Too many stages has a negative impact on delay
5
Example of Inverter (Buffer) Staging
1
Cg,1 = 1
Cg,1 = 1
CL = 64 Cg,1
4
1
Cg,1 = 1
tp
1
64
65
2
8
18
3
4
15
4
2.8
15.3
16
Cg,1 = 1
1
f
CL = 64 Cg,1
8
1
N
2.8
CL = 64 Cg,1
8
22.6
CL = 64 Cg,1
Impact of Buffer Staging for Large CL
F ( = 1)
Unbuffered
Two Stage
Chain
Opt. Inverter
Chain
10
11
8.3
8.3
100
101
22
16.5
1,000
1001
65
24.8
10,000
10,001
202
33.1
• Impressive speed-ups with optimized cascaded
inverter chain for very large capacitive loads.
Design Challenge

Keep signal rise times < gate propagation delays.
» good for performance
» good for power consumption

Keeping rise and fall times of the signals of
approximately equal values is one of the major
challenges in - slope engineering.
Power Dissipation
Power Dissipation
•Power consumption determines heat dissipation and energy
consumption
•Power influences design decisions:
•packaging and cooling
•width of supply lines
•power-supply capacity
•# of transistors integrated on a single chip
Power requirements make high density bipolar ICs
impossible (feasibility, cost, reliability)
Power Dissipation
Supply-line
sizing
Battery drain,
cooling
Power Dissipation
•Ppeak = static power + dynamic power
•Dynamic power:
•(dis)charging capacitors
•temporary paths from VDD to VSS
•proportional to switching frequency
•Static power:
•static conductive paths between rails
•leakage
•increases with temperature
Power Dissipation
•Propagation delay is related to power consumption
•tp determined by speed of charge transfer
•fast charge transfer => fast gate
•fast gate => more power consumption
•Power-delay product (PDP)
•quality measure for switching device
•PDP = energy consumed /gate / switching event
•measured using ring oscillator
Power Dissipation
Supply-line
sizing
Battery drain,
cooling
Energy consumed /gate /switching
event
CMOS Inverter: Steady State Response
•CMOS technology:
•No path exists between VDD and VSS in steady state
•No static power consumption! (ideally)
•Main reason why CMOS replaced NMOS
•NMOS technology:
•Has NMOS pull-up device that is always ON
•Creates voltage divider when pull-down is ON
•Power consumption limits # devices / chip
Dynamic Power Dissipation
Vdd
Vin
Vout
CL
Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f
Not a function of transistor sizes!
Need to reduce CL, Vdd, and f to reduce power.
Modification for Circuits with Reduced Swing
Vdd
Vdd
Vdd -Vt
CL
E 0  1 = CL  Vdd  ( Vdd – Vt )
Can exploit reduced sw ing to low er power
(e.g., reduced bit-line swing in memory)
Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
E
= C  V 2  n (N )
N
L
dd
EN : the energ y consumed for N clock cycles
n(N ): the number o f 0->1 transition in N clock cycles
EN
2
n (N )
P
= lim --------  f
=  lim ------------   C  V
 f clk
a vg N
clk
dd


N
N
N

L
0
P
1
=
n( N )
lim -----------N N
= 
C V 2f

av g
01
dd
clk
L
Short Circuit Currents
Vd d
Vin
Vout
CL
IVDD (mA)
0.15
0.10
0.05
0.0
1.0
2.0
3.0
Vin (V)
4.0
5.0
How to keep Short-Circuit Currents Low?
Short circuit current goes to zero if tout_fall >> tin_rise,
but can’t do this for cascade logic.
Minimizing Short-Circuit Power
8
7
Vdd =3.3
6
Vdd =2.5
Pnorm
5
4
3
Vdd =1.5
2
1
0
0
1
2
3
4
5
t /t
sin sout
Keep the input and output rise/fall times equal
If VDD<Vth+|Vtp| then short circuit power can be eliminated
Leakage
Vd d
Vout
Drain Junction
Leakage
Sub-Threshold
Current
Sub-threshold
currents rise exponentially
Sub-Threshold Current Dominant Factor
with temperature.
Reverse-Biased Diode Leakage
GATE
p+
p+
N
Reverse Leakage Current
+
V
- dd
IDL = JS  A
JS = 10-100 pA/mm2 at 25 deg C for 0.25mm CMOS
2
JS = 1-5pA/
for a 91.2deg
JS doubles
formm
every
C! technology
mm CMOS
Js double with every 9oC increase in temperature
Subthreshold Leakage Component
Static Power Consumption
Vd d
Istat
Vout
Vin =5V
CL
Pstat = P(In=1).Vdd . Istat
• Dominates over dynamic consumption
• Not a function of switching frequency