Dynamic Logic

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Transcript Dynamic Logic

Static Logic vs. Pseudo-nMOS
Static Logic includes pull-up and pull-down networks - 2n transistors for n-input
function.
weak
Pseudo-nMOS - n+1 transistors for n-input function
Requires pull-up transistor be weaker than pull-down network (5:1)
May eliminate p-transistors & possibly long pull-up chains
Static power dissipation
Pseudo-pMOS similar, except entirely out of p-transistors (good for NANDs)
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Building weak transistors
Weakening transistors requires reducing width, increasing length (R=L/W)
Create transistor with at least 5x greater resistance than others it fights against
R=10/3
R=2/3
R=2/15
A
Vdd
R=10/3, less load on signal A
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Dynamic Logic
Like pseudo-nMOS except don't always pull up
precharge
precharge
Initially charge output capacitance
Need to make sure pull-down isn't fighting it
Selectively discharge through pull-down network
Avoids static power dissipation (and is faster), but more dynamic power
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Charge Sharing
Redistribution of charge can degrade or change values
A
Precharge
Solution is to also precharge internal nodes
precharge
precharge
Note: Moves late-arriving
signals closer to output
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Charge Leakage
Compensate for leaking charge on output
Advantages of dynamic logic (less transistors) but has static power dissipation
Can avoid static power dissipation with inverter
precharge
weak
precharge
weak
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Domino Logic
Blocks in pseudo-nMOS style with inverter on output (non-inverting logic)
Precharging all blocks - outputs equal to 0
Ensures no other pull-down networks are interfering with precharging
When precharging is completed dominoes begin falling from first stage to last
Final result is some output stay low while others go high
precharge
pull-down
network
precharge
pull-down
network
precharge
pull-down
network
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Zipper Logic
Alternating blocks of n-type and p-type networks (provides an inversion)
By alternating stages, during precharge each gate's network is turned off by
precharge of previous stage
Similar to domino but transistors are easier to pack since there are equal
numbers of each type on average
precharge
pull-down
network
pull-up
network
precharge
precharge
pull-down
network
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Static vs. Dynamic Logic
Static
+ no charge sharing problems
+ no charge leakage problems
+ no static power dissipation
- 2n transistors
- series transistors always exist (slower)
Dynamic
+ n+1 transistors
- charge sharing
- charge leakage
- can have static power dissipation
+ potentially faster (eliminate series transistors)
- more complex control (generate precharge signal)
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