Transcript Seminar on High-Speed Asynchronous Pipelines

Clockless Logic
Montek Singh
Tue, Mar 16, 2004
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Outline
 Where are we?
 Recap: Logic Gate Families
 New Topic: Asynchronous Pipelined Processing
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Where are we?
 Introduction to clockless logic
 Benefits and challenges
 Data representation, and control signaling
 Graphical representation of asynchronous systems
 Petri nets, state transition graphs, burst-mode machines, etc.
 Algorithms for logic synthesis
 Combinational & Sequential
 VLSI design primer
Design techniques
 High-performance: fine-grain pipelining
 Low-power
 Formal methods
 Performance analysis
 Verification
 Case studies of real-world asynchronous processors
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Review:
Logic Gate Families
 Static CMOS logic
 Dynamic logic, or “domino” logic
 Transmission gates, or “pass-transistor” logic
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Static CMOS logic
Advantages:
 output always strongly driven
 pull-up and pull-down networks are fully-complementary;
exactly one of them is “on” always
 good immunity from noise and leakage
 both inverting and non-inverting functions implementable
 each gate is inverting
 cascade two gates together to get non-inverting logic
Disadvantages:
 slow/big PMOS devices needed (in addition to NMOS)
 greater chip area
 higher power consumption
 slower switching speed
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Dynamic Logic, or “domino”
Key idea:
 only use NMOS’s to compute function
 use a single PMOS to reset
Advantages:
 significantly fewer transistors  smaller chip area
 higher speed, lower power
 less “loading” on wires (drive fewer transistors)
 for async: no storage elements needed
Disadvantages:
 need extra control input to precharge
 logic is typically non-inverting only
 more vulnerable to noise and leakage effects
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Dynamic Logic, or “domino” (contd.)
Gate has 2 phases:
 precharge (=reset): output reset to ‘0’
 evaluate: output computed  either stays ‘0’, or switches to ‘1’
control input
PC
data
inputs
pull-up
network
pull-down
network
controls
“precharge”
data
output
controls
“evaluation”
PC =0 (asserted)
 precharge
PC =1 (de-asserted)
 evaluate
Pull-up and pull-down must never both be simultaneously active:
 ensure that data inputs are reset while gate is precharging
 or, add a “footer” device
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Transmission Gates
Key Idea:
 transistors used in a different configuration
 when switched on: instead of connecting output to Vdd or
Gnd, they connect output to the input
Advantage:
 very efficient for implementing switches and multiplexers
Disadvantage:
 signal degradation unless both NFET and PFET passgates are
used in a complementary configuration
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Asynchronous Pipelined Processing
 Pipelining basics
 Fine-grain pipelining
 Approach I: MOUSETRAP pipelines
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Background: Pipelining
What is Pipelining?: Breaking up a complex operation on a
stream of data into simpler sequential operations
fetch
decode
execute
A “coarse-grain” pipeline (e.g. simple processor)
Storage elements
(latches/registers)
A “fine-grain” pipeline (e.g. pipelined adder)
Performance Impact:
+ Throughput: significantly increased (#data items processed/second)
– Latency: somewhat degraded (#seconds from input to output)
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Focus of Asynchronous Community
Our Focus: Extremely fine-grain pipelines
 “gate-level” pipelining = use narrowest possible stages
 each stage consists of only a single level of logic gates
 some of the fastest existing digital pipelines to date
Application areas:
 general-purpose microprocessors
 instruction pipelines: often 20-40 stages
 multimedia hardware (graphics accelerators, video DSP’s, …)
 naturally pipelined systems, throughput is critical; input “bursty”
 optical networking
 serializing/deserializing FIFO’s
 string matching?
 KMP style string matching: variable skip lengths
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