Transcript Lecture 3 - CMOS Transistor Theory

Lecture 3:
CMOS
Transistor
Theory
Outline





Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics
Gate and Diffusion Capacitance
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
2
Goal of this section
 Present intuitive understanding of device
operation
 Introduction of basic device equations
 Introduction of models for manual
analysis
 Introduction of models for SPICE
simulation
 Future trends
CMOS VLSI Design 4th Ed.
Diodes
 Diodes do not appear in CMOS digital design as
separate devices.
 However, they are present as junctions and parasitic
elements in all devices.
 We will use a simple 1D analysis.
 We will not concern ourselves too much with the DC
behavior too much.
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
4
Depletion Region
hole diffusion
electron diffusion
(a) Current flow.
n
p
hole drift
electron drift
Charge
Density

x
Distance
+
-
Electrical
Field
(b) Charge density.

x
(c) Electric field.
x
(d) Electrostatic
potential.
V
Potential
-W 1

W2
CMOS VLSI Design 4th Ed.
DC Characteristics
N A N D 
 0  T ln  2 
 n i 
kT
T 
 25.8mV
q

3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
6
Diode Current
CMOS VLSI Design 4th Ed.
pn (W2)
Forward Bias
pn0
Lp
np0
p-region
-W1 0
W2
n-region
diffusion
Typically avoided in Digital ICs
CMOS VLSI Design 4th Ed.
x
Reverse Bias
pn0
np0
p-region
-W1 0
W2
x
n-region
diffusion
The Dominant Operation Mode
CMOS VLSI Design 4th Ed.
Models for Manual Analysis
+
ID = IS(eV D/T – 1)
VD
ID
+
+
VD
–
(a) Ideal diode model
–
VDon
–
(b) First-order diode model
CMOS VLSI Design 4th Ed.
Junction Capacitance
Q j  AD
W 

N A N D 
2 Siq
  VD 
n i2  0

2 Si N A  N D
0  VD 
q NA ND
2q N A N D 
 j  
0  VD 

N

N
 Si A
D 
Cj 
Cj 
q N  N D 
dQ j
1
 AD  Si A
 0  VD 
dVD
 2 N A N D 
C j0
1
VD
where
0
q N  N D  1
C j 0  AD  Si A
0 
2
N
N

A D 
3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.
11
Junction Capacitance
CMOS VLSI Design 4th Ed.
Junction Capacitance
 m is known as the grading coefficient.
 Keep in mind that Cj is a small signal parameter. For
large signal switching, an equivalent capacitance
has to be calculated as
 
Q j Q Vhigh  QVlow 
Ceq 

 K eq C j 0
VD
Vhigh  Vlow
 Ceq has been defined such that the same amount of
charge is transferred as the nonlinear model

K eq 
V
0m
high  Vlow
3: CMOS Transistor Theory

0 Vhigh


1  m



1m 
CMOS VLSI Design 4th Ed.
1m 
 0  Vlow 


13
Junction Capacitance
 As a numerical example, a diode is switched
between 0 and -2.5 V. The diode has Cj0 = 2 X 10-3
F/m2, AD = 0.5 (mm)2, F0 = 0.64 V, m = 0.5.
 Keq = 0.622, Ceq = 1.24 fF/(mm)2.
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
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Diffusion Capacitance
CMOS VLSI Design 4th Ed.
Diffusion Capacitance
 Effective in forward bias
Qp  qAD
Wn
 p x  p dx
n
n0
W2
 VD 

T
W n  W 2 pn 0e 1
 qAD
2
W n2

I  Tp IDp
2Dp Dp
ID 
3: CMOS Transistor Theory

Qp
Tp

Qn
Tn

QD
T
CMOS VLSI Design 4th Ed.
16
Diffusion Capacitance
 From this lifetime analysis of excess charge,
dQD
dID T ID
Cd 
 T

dVD
dVD
T
 Note that Cd is also a small signal capacitance
 

QD T ID Vhigh  ID Vlow 
Ceq 

VD
Vhigh  Vlow

Cd high   Cd low 

T
Vhigh  Vlow

3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
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Other Diode Parameters
 Secondary Effects
– Resistivity of regions outside junction
– Breakdown voltage
– Temperature dependence
 FT has a linear dependence
• IS doubles every 8˚C
• Overall, current doubles every 12˚C.
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
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SPICE Model
 The following summarize diode behavior:
 VD n

T
ID  IS e
1


T I S V
CD 
e
T
D
n T

C j0
 VD m
1 

 0 

 n is called the emission coefficient and concentrates
thenon-idealities listed above.
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
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SPICE Parameters
CMOS VLSI Design 4th Ed.
Introduction
 So far, we have treated transistors as ideal switches
 An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
– I = C (V/t) -> t = (C/I) V
– Capacitance and current determine speed
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
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MOS Capacitor
 Gate and body form MOS
capacitor
V <0
 Operating modes
+
– Accumulation
– Depletion
(a)
– Inversion
0<V <V
g
g
polysilicon gate
silicon dioxide insulator
p-type body
t
+
-
depletion region
(b)
Vg > Vt
+
-
inversion region
depletion region
(c)
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
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Terminal Voltages
Vg
 Mode of operation depends on Vg, Vd, Vs
+
+
– Vgs = Vg – Vs
Vgs
Vgd
– Vgd = Vg – Vd
Vs
Vd
– Vds = Vd – Vs = Vgs - Vgd
+
Vds
 Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds  0
 nMOS body is grounded. First assume source voltage is 0 too.
 Three regions of operation
– Cutoff
– Linear (Resistive)
– Saturation (Active)
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
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nMOS Cutoff
 No channel
 Ids ≈ 0
Vgs = 0
g
+
-
+
-
s
d
n+
n+
Vgd
p-type body
b
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
24
nMOS Linear
 Channel forms
 Current flows from d to s
V
– e from s to d
 Ids increases with Vds
 Similar to linear resistor
gs
> Vt
g
+
-
+
-
s
d
n+
n+
Vgd = Vgs
Vds = 0
p-type body
b
Vgs > Vt
g
+
s
+
d
n+
n+
Vgs > Vgd > Vt
Ids
0 < Vds < Vgs-Vt
p-type body
b
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
25
nMOS Saturation




Channel pinches off
Ids independent of Vds
We say current saturates
Similar to current source
Vgs > Vt
g
+
-
+
-
Vgd < Vt
d Ids
s
n+
n+
Vds > Vgs-Vt
p-type body
b
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
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I-V Characteristics
 In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
27
Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversions
– Gate – oxide – channel
 Qchannel = CV
Cox = ox / tox
 C = Cg = oxWL/tox = CoxWL
 V = Vgc – Vt = (Vgs – Vds/2) – Vt
gate
Vg
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.9)
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
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Carrier velocity
 Charge is carried by e Electrons are propelled by the lateral electric field
between source and drain
– E = Vds/L
 Carrier velocity v proportional to lateral E-field
– v = mE
m called mobility
 Time for carrier to cross channel:
– t=L/v
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
29
nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds 
t
W
 mCox
L
V  V  Vds
 gs t
2

V
  Vgs  Vt  ds Vds
2

3: CMOS Transistor Theory
V
 ds

CMOS VLSI Design 4th Ed.
W
 = mCox
L
30
nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current
Vdsat

I ds   Vgs  Vt 
2



V

2
gs
 Vt 
3: CMOS Transistor Theory
V
 dsat

2
CMOS VLSI Design 4th Ed.
31
nMOS I-V Summary
 Shockley 1st order transistor models


0

 
Vds
I ds    Vgs  Vt 
2


2


Vgs  Vt 


2
3: CMOS Transistor Theory
Vgs  Vt
V V  V
 ds
ds
dsat

Vds  Vdsat
CMOS VLSI Design 4th Ed.
cutoff
linear
saturation
32
Example
 Your book will be using a 0.6 mm process
– From AMI Semiconductor
– tox = 100 Å
2.5
V =5
2
– m = 350 cm /V*s
2
– Vt = 0.7 V
1.5
V =4
 Plot Ids vs. Vds
1
V =3
– Vgs = 0, 1, 2, 3, 4, 5
0.5
V =2
– Use W/L = 4/2 l
V =1
0
Ids (mA)
gs
gs
gs
gs
gs
0
 3.9  8.85 1014   W
W
  mCox   350  

8
L
 100 10
 L
3: CMOS Transistor Theory
1
W


120
μA/V 2

L

CMOS VLSI Design 4th Ed.
2
3
4
5
Vds
33
pMOS I-V
 All dopings and voltages are inverted for pMOS
– Source is the more positive terminal
 Mobility mp is determined by holes
– Typically 2-3x lower than that of electrons mn
– 120 cm2/V•s in AMI 0.6 mm process
 Thus pMOS must be wider to
provide same current
– In this class, assume
mn / mp = 2
0
Vgs = -1
Vgs = -2
-0.2
Ids (mA)
Vgs = -3
-0.4
Vgs = -4
-0.6
-0.8
-5
Vgs = -5
-4
-3
-2
-1
0
Vds
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
34
Capacitance
 Any two conductors separated by an insulator have
capacitance
 Gate to channel capacitor is very important
– Creates channel charge necessary for operation
 Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
35
Level 1 Implementation in SPICE
 Including the channel length modulation, body effect
and overlaps,
ID 
m SiO
2
t ox
W 
VDS 
V

V

 GS
VDS resistive
T
L  2LD 
2 
m SiO
2


W
V

V
T
2
ID 
 GS
 1 lVDS  active
t ox L  2LD  2 
1
VT  VFB   S 
2q SiN A S  VSB
Cox
VT  VFB   S    S  VSB
VT  VT 0  
3: CMOS Transistor Theory

V
SB
 S  S

CMOS VLSI Design 4th Ed.
36
The Body Effect
0.9
0.85
0.8
0.75
VT (V)
0.7
0.65
0.6
0.55
0.5
0.45
0.4
-2.5
-2
-1.5
-1
V
BS
(V)
CMOS VLSI Design 4th Ed.
-0.5
0
SPICE Model
Name
Symbol
SPICE
Name
Type
Lateral Diffusion
LD
LD
Physical
Oxide Thickness
tox
TOX
Physical
Channel length modulation
l
LAMBDA
Physical
Surface Mobility
m
U0
Physical
Substrate Doping
NA
NSUB
Physical
Current Parameter
kp
KP
Electrical
Work Function
S
PHI
Electrical
Threshold Voltage
VT0
VTO
Electrical
Body Effect Parameter

GAMMA
Electrical
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
38
SPICE Model
 Electrical parameters override when provided.
 Otherwise, they are calculated from physical
parameters.
 LAMBDA is an empirical parameter.
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
39
Level 2 Implementation in SPICE
 Now, let us remove some of the wrong assumptions.
 Voltage across channel is not constant any more
 The threshold voltage is not a constant any more
VT Vc   VFB   S    S  VSB  Vc
Vc  Vc y 
m
dVc
dy

dy Q
ID
L
I
0
D
dy  mCoxW
VDS
 V
GS
 VT  Vc dVc
0
3
3 
W 
VDS 
2 
2
ID  mCox VGS  VFB   S 
VDS   VDS  VSB   S    S  VSB  2 

L 
2 
3 
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
40
Level 2 Implementation in SPICE
 To find the equation in the active region, take the
derivative of ID and equate to 0.
 VDS = VDS,sat when ID is maximum.
VDS,sat  VGS  VFB
1 
 
 2
2
2 
  S   1  1 2 VGS  VFB  

 
  

ID,act  ID VDS  VDS,sat 
 Note that ID is dependent on  even if VSB = 0.
 VT is not explicitly used in the equations.

3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
41
More Corrections
 Mobility is reduced with increasing gate voltage.
– We will study this effect in detail later.
 Current conduction occurs below the threshold
voltage.
– We will study this effect later.
 Channel length modulation has to be corrected.
 Threshold voltage depends on W and L.
 Parasitic resistances in the source and drain
 Latchup
 Speed limit of carriers
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
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Speed Limit of Carriers
 Ohm’s Law is not true
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
43
Speed Limit of Carriers
 Velocity is proportional to electric field for low fields
v  mn
 Velocity is saturated for high fields
v  v sat
 To ensure
 continuity, use the following
approximation for velocity.
v

 Then,
ID 

3: CMOS Transistor Theory
m n

1
c
,
mn Cox
1
VDS
c L
c 
2v sat
mn
2 
W 
VDS
V  VT VDS 

L  GS
2 
CMOS VLSI Design 4th Ed.
44
Speed Limit of Carriers
 That equation is still too complex for hand analysis.
 Substitute the values at the critical electric field to
find the current at the transition point.
c 
2v sat
mn
2 
2v sat L
W 
VDS
ID VDS,sat  
mn Cox VGS  VT VDS 

mnVDS
L 
2 

VDS,sat 
 2v satCoxW VGS  VT 


2 
 An even simpler approach is as follows
v  mn for   E c
VDS,sat  L c 

and
v  v sat  mn c
for    c
Lv sat
mn


V
ID,sat  ID VDS  VDS,sat   v satCoxW VGS  VT  DS,sat 

2 
3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.
45
A Unified Model for Manual Analysis
CMOS VLSI Design 4th Ed.
Transistor Model for Manual Analysis
CMOS VLSI Design 4th Ed.
The Transistor as a Switch
VGS  V T
Ron
S
ID
V GS = VD D
D
Rmid
R0
V DS
VDD/2
CMOS VLSI Design 4th Ed.
VDD
Drain-Source Resistance
 Large signal drain-source resistance is a nonlinear
quantity varying across operating regions.
 One can define an equivalent resistance
1
Req 
t 2  t1
Vds t 
 I t dt
d
t1
t2
 For a weakly nonlinear function,

3: CMOS Transistor Theory
1 Vds t1 Vds t 2 

Req  

2 
Id t1 Id t 2  

CMOS VLSI Design 4th Ed.
49
Drain-Source Resistance
 Applying the general formula for a transistor
switching from VDD to VDD/2,

3 VDD  7
Req 
1  lVDD 

4 ID,sat  9
 Alternatively, using the endpoints and averaging,


3: CMOS Transistor Theory

3 VDD  5
Req 
1  lVDD 

4 ID,sat  6
CMOS VLSI Design 4th Ed.
50
Drain-Source Resistance
7
x 10
5
6
Req (Ohm)
5
4
3
2
1
0
0.5
1
1.5
V
DD
2
(V)
CMOS VLSI Design 4th Ed.
2.5
Drain-Source Resistance
CMOS VLSI Design 4th Ed.
Drain-Source Resistance
 Note the following
– R is inversely proportional to W/L
– For VDD >> VT + VD,sat/2, R is independent of VDD.
– When VDD is close to VT, resistance increases.
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
53
MOS Capacitances
G
CGS
CGD
D
S
CGB
CSB
CDB
B
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
54
Gate Capacitance
 Approximate channel as connected to source
 Cgs = oxWL/tox = CoxWL = CpermicronW
 Cpermicron is typically about 2 fF/mm
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.90)
p-type body
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
55
Gate Capacitance
Operation Region
Cgb
Cgs
Cgd
Cut-off
CoxWLeff
Cov
Cov
Resistive
0
CoxWLeff/2 + Cov
CoxWLeff/2 + Cov
Active
0
(2/3) CoxWLeff + Cov
Cov
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
56
Diffusion Capacitance
 Csb, Cdb
 Undesirable, called parasitic capacitance
 Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
57
Capacitances in 0.25 mm CMOS Process
CMOS VLSI Design 4th Ed.
Sub-Threshold Conduction
-2
10
The Slope Factor
Linear
-4
10
I D ~ I 0e
-6
, n  1
CD
Cox
Quadratic
ID
(A)
10
S is VGS for ID2/ID1 =10
-8
10
-10
Exponential
-12
VT
10
10
qVGS
nkT
0
0.5
1
1.5
VGS (V)
2
2.5
Typical values for S:
60 .. 100 mV/decade
CMOS VLSI Design 4th Ed.
Sub-Threshold ID vs VGS
I D  I 0e
qVGS
nkT
qV
 DS

1  e kT






VDS from 0 to 0.5V
CMOS VLSI Design 4th Ed.
Sub-Threshold ID vs VDS
I D  I 0e
qVGS
nkT
qV
 DS

1  e kT



1  l  VDS 


VGS from 0 to 0.3V
CMOS VLSI Design 4th Ed.
Scaling
Parameter
Relation
Full Scaling
Fixed V
scaling
General
Scaling
W, L, tox
-
1/S
1/S
1/S
VDD, VT
-
1/S
1
1/U
NSUB
V/W2depl
S
S2
S2/U
Area/Device
WL
1/S2
1/S2
1/S2
Cox
1/tox
S
S
S
Cgate
CoxWL
1/S
1/S
1/S
kn, kp
CoxW/L
S
S
S
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
62
Scaling (Continued)
Parameter
Relation
Full Scaling
Fixed V
Scaling
General
Scaling
ID,sat
CoxWV
1/S
1
1/U
Current
Density
ID,sat/Area
S
S2
S2/U
Ron
V/ID,sat
1
1
1
Intrinsic
Delay
RonCgate
1/S
1/S
1/S
Power
ID,satV
1/S2
1
1/U2
Power
Density
Power/Area
1
S2
S2/U2
3: CMOS Transistor Theory
CMOS VLSI Design 4th Ed.
63