Transcript Lecture 12-power-examples

Lecture 7:
Power
Activity Factor Estimation
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Activity factor: probability a that a node switches 0→1
Define probability Pi that a node is “1”
Probability that a node is “0” is then Pi = 1-Pi
ai = Pi * Pi
Completely random data has P = 0.5 and a = 0.25
Data is often not completely random
Data propagating through ANDs and ORs has lower
activity factor
– Depends on design, but typically a ≈ 0.1
7: Power
CMOS VLSI Design 4th Ed.
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Switching Probability
7: Power
CMOS VLSI Design 4th Ed.
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Example
 A 4-input AND is built out of two levels of gates
 Estimate the activity factor at each node if the inputs
have P = 0.5
NAND: If A and B are ”ones” there will be a ”0” output: PNAND=1-PAPB
NOR: If n1 and n2 are ”zeroes” there will be a ”1” output: PNOR=P1P2
NAND
NOR
NAND
7: Power
CMOS VLSI Design 4th Ed.
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ON and OFF Current
 Ion = Ids @ Vgs = Vds = VDD
– Saturation
Ids (A)
1000
Ion = 747 mA @
Vgs = Vds = VDD
800
Vgs = 1.0
600
Vgs = 0.8
400
Vgs = 0.6
200
Vgs = 0.4
0
Vds
0
0.2
0.4
0.6
0.8
1
 Ioff = Ids @ Vgs = 0, Vds = VDD
– Cutoff
4: Nonideal Transistor Theory
CMOS VLSI Design 4th Ed.
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Leakage Sources
 Subthreshold conduction
– Transistors can’t abruptly turn ON or OFF
– Dominant source in contemporary transistors
 Gate leakage
– Tunneling through ultrathin gate dielectric
 Junction leakage
– Reverse-biased PN junction diode current
4: Nonideal Transistor Theory
CMOS VLSI Design 4th Ed.
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Leakage
 What about current in cutoff?
 Simulated results
 What differs?
– Current doesn’t
go to 0 in cutoff
4: Nonideal Transistor Theory
CMOS VLSI Design 4th Ed.
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DIBL
 Electric field from drain affects channel
 More pronounced in small transistors where the
drain is closer to the channel
 Drain-Induced Barrier Lowering
VVV  
– Drain voltage also affect Vt
ttds
V t   V t   V ds
 High drain voltage causes current to increase.
4: Nonideal Transistor Theory
CMOS VLSI Design 4th Ed.
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Threshold Voltage Effects
 Vt is Vgs for which the channel starts to invert
 Ideal models assumed Vt is constant
 Really depends (weakly) on almost everything else:
– Body voltage: Body Effect
– Drain voltage: Drain-Induced Barrier Lowering
– Channel length: Short Channel Effect
4: Nonideal Transistor Theory
CMOS VLSI Design 4th Ed.
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Body Effect
 Body is a fourth transistor terminal
 Vsb affects the charge required to invert the channel
– Increasing Vs or decreasing Vb increases Vt
Vt  Vt 0  g

f s  V sb  f s

 fs = surface potential at threshold
f s  2 v T ln

NA
ni
– Depends on doping level NA
– And intrinsic carrier concentration ni
g = body effect coefficient
g 
t ox
 ox
2 q  si N A 
4: Nonideal Transistor Theory
2 q  si N A
C ox
CMOS VLSI Design 4th Ed.
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Body Effect
 Body is a fourth transistor terminal
 Vsb affects the charge required to invert the channel
– Increasing Vs or decreasing Vb increases Vt
Vt  Vt 0  g

f s  V sb  f s

 fs = surface potential at threshold
f s  2 v T ln

NA
ni
– Depends on doping level NA
– And intrinsic carrier concentration ni
g = body effect coefficient
g 
t ox
 ox
2 q  si N A 
4: Nonideal Transistor Theory
2 q  si N A
C ox
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Body Effect Cont.
 For small source-to-body voltage, treat as linear
4: Nonideal Transistor Theory
CMOS VLSI Design 4th Ed.
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Gate Leakage
 Carriers tunnel thorough very thin gate oxides
 Exponentially sensitive to tox and VDD
– A and B are tech constants
– Greater for electrons
• So nMOS gates leak more
 Negligible for older processes (tox > 20 Å)
 Critically important at 65 nm and below (tox ≈ 10.5 Å)
From [Song01]
4: Nonideal Transistor Theory
CMOS VLSI Design 4th Ed.
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Subthreshold Leakage
 Subthreshold leakage exponential with Vgs
V gs  V t 0   V ds  k g V sb
I ds  I ds 0 e
nvT
 V ds

v
1  e T






 n is process dependent
– typically 1.3-1.7
 Rewrite relative to Ioff on log scale
 S ≈ 100 mV/decade @ room temperature
4: Nonideal Transistor Theory
CMOS VLSI Design 4th Ed.
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Subthreshold Leakage
 For Vds > 50 mV
V gs   V ds  V D D   k g V sb
I sub  I off 10
S
 Ioff = leakage at Vgs = 0, Vds = VDD
7: Power
Typical values in 65 nm
Ioff = 100 nA/m @ Vt = 0.3 V
Ioff = 10 nA/m @ Vt = 0.4 V
Ioff = 1 nA/m @ Vt = 0.5 V
 = 0.1
kg = 0.1
S = 100 mV/decade
CMOS VLSI Design 4th Ed.
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Stack Effect
 Series OFF transistors have less leakage
– Vx > 0, so N2 has negative Vgs
 V x V D D
I sub  I off 10
 V x   V D D  V x   V D D   k g V x

S
 I off 10
S
N1
Vx 
N2
VDD
1  2  k g
I sub  I off 10
 1   k g
 V D D 
 1  2  k
g

S




 V D D
 I off 10
S
– Leakage through 2-stack reduces ~10x
– Leakage through 3-stack reduces further
7: Power
CMOS VLSI Design 4th Ed.
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NAND3 Leakage Example
 100 nm process
Ign = 6.3 nA
Igp = 0
Ioffn = 5.63 nA Ioffp = 9.3 nA
Data from [Lee03]
7: Power
CMOS VLSI Design 4th Ed.
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Lecture 10:
Circuit
Families
CMOS VLSI Design 4th Ed.
Outline
 Pseudo-nMOS Logic
 Dynamic Logic
 Pass Transistor Logic
10: Circuit Families
CMOS VLSI Design 4th Ed.
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Introduction
 What makes a circuit fast?
– I = C dV/dt -> tpd  (C/I) DV
– low capacitance
– high current
4
B
– small swing
4
A
 Logical effort is proportional to C/I
1
1
 pMOS are the enemy!
– High capacitance for a given current
 Can we take the pMOS capacitance off the input?
 Various circuit families try to do this…
10: Circuit Families
CMOS VLSI Design 4th Ed.
Y
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Pseudo-nMOS
 In the old days, nMOS processes had no pMOS
– Instead, use pull-up transistor that is always ON
 In CMOS, use a pMOS that is always ON
– Ratio issue
– Make pMOS about ¼ effective strength of
pulldown network
1.8
1.5
load
P/2
1.2
P = 24
Ids
Vout 0.9
Vout
16/2
Vin
0.6
P = 14
0.3
P=4
0
0
0.3
0.6
0.9
1.2
1.5
1.8
Vin
10: Circuit Families
CMOS VLSI Design 4th Ed.
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Dynamic Logic
 Dynamic gates uses a clocked pMOS pullup
 Two modes: precharge and evaluate
2
A
f
2/3
Y
1
Y
1
A
Static
4/3
Pseudo-nMOS
f
Precharge
Y
A
1
Dynamic
Evaluate
Precharge
Y
10: Circuit Families
CMOS VLSI Design 4th Ed.
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The Foot
 What if pulldown network is ON during precharge?
 Use series evaluation transistor to prevent fight.
precharge transistor
f
Y
f
f
Y
inputs
A
Y
inputs
f
f
foot
footed
10: Circuit Families
CMOS VLSI Design 4th Ed.
unfooted
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Monotonicity
 Dynamic gates require monotonically rising inputs
during evaluation
f
– 0 -> 0
A
– 0 -> 1
– 1 -> 1
violates monotonicity
– But not 1 -> 0
during evaluation
A
f
Precharge
Evaluate
Precharge
Y
Output should rise but does not
10: Circuit Families
CMOS VLSI Design 4th Ed.
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Monotonicity Woes
 But dynamic gates produce
monotonically falling
outputs during evaluation
 Illegal for one dynamic gate
to drive another!
A=1
f
A
Y
f
Precharge
Evaluate
Precharge
X
X
X monotonically falls during evaluation
Y
Y should rise but cannot
10: Circuit Families
CMOS VLSI Design 4th Ed.
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Domino Gates
 Follow dynamic stage with inverting static gate
– Dynamic / static pair is called domino gate
– Produces monotonic outputs
f
Precharge
Evaluate
Precharge
domino AND
W
W
X
Y
Z
X
A
B
C
f
Y
Z
dynamic static
NAND inverter
f
A
B
10: Circuit Families
f
f
W
X
H
C
CMOS VLSI Design 4th Ed.
Y
H
Z
=
A
B
f
X
Z
C
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Charge Sharing
 Dynamic gates suffer from charge sharing
f
f
A
Y
CY
x
A
Y
B=0
Cx
Charge sharing noise
x
V x  VY 
10: Circuit Families
CMOS VLSI Design 4th Ed.
CY
C x  CY
V DD
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