Transcript CS 2204 Fall 2005 - NYU Polytechnic School of Engineering

CS 2204
Lab 5
Digital Logic
and
State Machine Design
As you wait for the lab to start :
 Is your laptop up-to-date ?
Experiments 1-2
Spring 2014

Experiments 1 - 2 Lab 5 Outline
 Presentation

Using General Design Rules

Using A Brief Look at Semiconductor Technology

Using Term Project (pages 22 - 30)
 General Design Rules
 Gate Features
 A comparison of CMOS, TTL and ECL
 Analysis of the term project
• Analysis of Block 4 of the term project
• Machine playing strategies
 Individual work

Experiment 1 is over three weeks : Lab 3, Lab 4 and Lab 5

Experiment 2 is also today : Lab 5
 Develop a 4-bit 2-to-1 MUX of Block 2
 Develop a 4-bit Adder of Block 4
• Use the Algebraic Simplifications Handout to design it

New handout
 General Design Rules
CS 2204 Spring 2014 Experiment 1-2 Lab 5
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
General Design Rules
 How would you approach

Design
 System design ?
Problem Solving ?
 Being systems oriented ?
 Pressure-filled tasks ?

 If you are in control of the task, you have a chance to
complete it successfully on time
• If the task is in control, the chances are slim !
 Useful for this course, until graduation and
after

Use them for exams, projects, homework, etc.
CS 2204 Spring 2014 Experiment 1-2 Lab 5
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
Goal : Be in control of the pressure-filled task
 Rule 1 : You have enough pressure in the beginning, do
not increase it further


Do not rush  Think  Help yourself
Prepare a mental/written plan to start and complete the
task which uses the remaining rules
 If it was an exam : You would not rush to solve the first
question !
• You would read all the questions and decide solving from the
easiest towards the most difficult
CS 2204 Spring 2014 Experiment 1-2 Lab 5
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
Goal : Be in control of the pressure-filled task
 Rule 2 : Keep your task simple in the beginning


Deal with simple concepts and few details in the beginning
Give yourself a chance to like the task in case you are not
motivated enough
 Ask yourself :
• Am I familiar with the system I will design ?
• Am I familiar with the design process ?
CS 2204 Spring 2014 Experiment 1-2 Lab 5
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
Goal : Be in control of the pressure-filled task
 Rule 2 : Keep your task simple in the beginning

If no to either one, do all or some of the following :
 Investigate similar systems and design processes, i.e. a
background search and use it if allowed
• If it was an exam, you would look at your notes, homework, handouts and
books to have an idea about the question
 Follow a top-down (block-based) design to deal with simple
concepts in the beginning (blocks and their input/output
relationship)
 If possible, design a representative piece of the system you
will design
• Design an 8-bit ADDer and then gradually expand it to the final goal of a
64-bit ADDer
• Design a 2-bit up/down counter first and then gradually expand it to the
final goal of a 8-bit up/down counter
CS 2204 Spring 2014 Experiment 1-2 Lab 5
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
Goal : Be in control of the pressure-filled task
 Rule 3 : Base your decisions on design goals : speed,
cost, power, reliability, size, weight, etc.


Such as selecting among alternative components
Be consistent
 Do not make decisions that look arbitrary

Use design goals even when you partition blocks
CS 2204 Spring 2014 Experiment 1-2 Lab 5
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
Goal : Be in control of the pressure-filled task
 Rule 4 : When you start the design, do not go for the
best design possible

Get a system that works first then, optimize it with respect
to the design goals.
 Thus, relax Rule 3 in the beginning
• Use this rule especially if you are a new designer
CS 2204 Spring 2014 Experiment 1-2 Lab 5
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
Goal : Be in control of the pressure-filled task
 Rule 5 : Your design must be such that one can
upgrade it in the future


Design such that there is room for future upgrades
Otherwise, to upgrade it would be impossible and so the
system has to be redesigned from scratch !
 The Ppm project is designed so that one can have different
versions of it
• Human vs. machine now
• Human vs. human later
• Machine vs. machine later
 A computer is designed so that in the future one can upgrade
• The memory to large sizes
• To a new version of the microprocessor
CS 2204 Spring 2014 Experiment 1-2 Lab 5
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
Goal : Be in control of the pressure-filled task
 Rule 6 : Design or at least consider more than one
layer at a time after you become familiar with the
system you are designing and the design process.

This is possible if you are an experienced designer
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 10

Goal : Be in control of the pressure-filled task
 Rule 7 : If you are stuck and does not know what to
do, especially does not know what to do next, STOP !

Move up to higher layers and see where you are
 You will see what you have missed
 You will see which (sub)block is next
CS 2204 Spring 2014 Experiment 1-2 Lab 5
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
Goal : Be in control of the pressure-filled task
 Rule 8 : If you cannot explain something, cannot
explain why it happens as it happens, “zoom in”

Move to the lower layers and focus on few (sub)blocks that
affect the situation
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 12

Xilinx Project Development Steps Today’s work
 Develop the schematic

Design the schematic
 Place the components and wires
 Do a schematic check

What are these
components ?
Test the schematic via logic simulations
 Do a Xilinx IMPLEMENTATION

It maps the components to the CLBs of the chip
 Do timing simulations to test the schematic

It generates the bit file
 Download the bit file to the FPGA and test the
design on the board

It programs the chip
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 13

Developing a digital product
 A new chip

Which gates & FFs and how many is determined by
 Available components of the technology chosen
 Besides the major operations and speed, cost, power, etc.
design goals of the digital product

FPGAs are used to test the new chip
 A new PCB

Which chips and how many is determined by
 Available chips of the technology chosen
 Besides the major operations and speed, cost, power, etc.
design goals of the digital product
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 14

Gate Features
 Speed, Cost, Power, Size,…

Determined by switch features
 Speed, cost, power, size,…
• Depend on the technology chosen
► CMOS, BiCMOS, TTL, ECL
 They have their own subfamilies
 CMOS : HC, HCT, AC, ACT, FCT,…
 TTL : H, L, S, LS, AS,…
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 15

Gate Speed
 It is defined in terms of the gate delay duration
 The gate delay duration is the time it takes for the gate output
to change after an input is changed

Gate delay, propagation delay : tp
 Measured in terms of picoseconds (10-12 seconds) today

Determined by
a
 The technology
• ECL is the fastest
• CMOS is the slowest
b
 The number of inputs
• The more inputs, the longer the delay
 The transistor size
y
• The smaller, the faster
a
b
y
tp
Today : In terms of picoseconds
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 16

Gate Speed
 Gate delays are sometimes good

Flip-flops are implemented by taking the advantage of gate
delays
 Without gate delays we could not implement flip-flops via gates
D FF implementation
via gates
D FF
From ON Semiconductor LS TTL Data Manual
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 17

Gate Speed
 Gate delays are often not good

The circuit output is delayed
 We do not have infinite speed

Glitches occur on the outputs
 Outputs change unexpectedly when an input is changed
• If outputs are used during the glitch time, erroneous results will
occur
 A glitch for a circuit happens only if a specific input
combination is applied first and then another specific input
combination is applied
• For all other input combination pairs, it does not happen
• For the 2-to-1 MUX the specific input combinations are 111 and
then 011
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 18

Gate delays result in glitches
a, b, c = 111
a, b, c = 011
 If ideal gates were used ?

No gate delays !
a
 No glitch !
1
0
1 0
a
a
ab
NOT
AND
1
a
b
1
0
1
1 1
y
1 0
c
a
ab
OR
AND
ac
1
0
ac
y
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 19

Gate delays result in glitches
1
0
1 0
a
a
ab
NOT
AND
b
a
1 0
c
The output
should not
be zero
momentarily
?
1 1
0
y
a
OR
AND
1
a
1
1
Do not use the output
during this time
ac
1
0
No !
1 0 1
Glitch
(timing hazard)
ac
ab
y
a, b, c = 111
a, b, c = 011
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 20

Gate Cost
 How much a gate costs : Pennies or less today

Determined by
 The technology
• ECL is the most expensive and TTL is the least
 The number of inputs
• The more inputs, the more expensive
 The number of gates on the chip
• More gates on the chip, the cheaper each gate is

Why are Chips Cheap Today ?
 Silicon is the most common semiconductor
• Sea sand has silicon
• Second most abundant element on earth, after oxygen !
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 21

Gate Power Consumption
 Amount of electrical power consumed by a single gate


Micro Watts or less today
Determined by
 The technology
• ECL is the most consuming and CMOS is the least
 The number of inputs
• The more inputs, the higher power consumption
 The speed of the switching elements (transistors)
• The higher the speed, the higher the power consumption
 The size of the switching elements (transistors)
• The smaller the size, the smaller the power consumption
 The higher the power consumption, the higher heat
generated

Indirectly determines the density of the chip
 The number of transistors on the chip
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 22

Gate Size
 How large a gate is


Nanometers on a side today
Determined by
 Transistor size
• A function of the process length ≡ 22 nanometer today
 Technology
• The type of the transistor (unipolar vs. bipolar)
• The number of supporting electronic components (resistors,
diodes, capacitors, etc.)
 The number of inputs
• The more inputs, the larger the gate is

Indirectly determines the density of the chip
 The number of transistors on the chip
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 23

Gate Size
 How large a gate is


Nanometers on a side today
Transistor size
~3*PL Transistor
~5*PL
 A function of the process length ≡ 22 nanometer today
• The distance between two wires
• Reason for Moore’s Law
PL ≡ Process Length
A transistor
~3*PL
Transistor
~5*PL
Nano size
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 24

Silicon Technology Today
The Intel Xeon E7 10-core
die with 2.6 Billion
transistors, 32 nm
Intel Xeon E7 wafer
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 25

Silicon Technology Today

A comparison of CMOS,TTL and ECL technologies
CMOS has
two wins
TTL has
one win
ECL has
one win
CMOS is the choice for high-density chips today !
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 26

Silicon Technology Today
 A brief comparison of CMOS and TTL technologies
From :
Semiconductor
Technology
handout
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 27

Silicon Technology Today
 The transistor size depends on process length
 There are chips with shorter process length now
 Micron 128-Gbit Flash memory : 16 nm (16x10-9 meter)
 Samsung 128 Gbit Flash memory : 19nm (19x10-9 meter)
Samsung 3-D Vertical
NAND
128Gbit Flash EPROM
memory with
45 Billion+ transistors
using 19nm process
Micron 128Gbit Flash memory
die with 64 Billion+ transistors
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 28

Silicon Technology Today
 The transistor size depends on process length
 Chips with shorter process length later this year
 Xilinx Virtex UltraScale, VU 440 : 20nm (20x10-9 meter)
• A 3-D chip : Multiple dice stacked up containing > 20 Billion
transistors
 Xilinx Virtex UltraScale : 16nm (16x10-9 meter)
A 3-D chip with 3-D transistors : FinFet transistors !
Xilinx VU 440
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 29

Silicon Technology Today
 The transistor size depends on process length
 Chips with shorter process length this year
 Altere Arria 10 FPGA chip : 20nm (20x10-9 meter)
• A 3-D chip with multiple dice stacked up
 Altera Stratix 10 FPGA chip : 14nm (14x10-9 meter)
A chip with 3-D transistors :
Intel FinFet transistors !
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 30

Silicon Technology Today
 The transistor size depends on process length
 The densest chips
28 nm process
28 nm process
First multi-dimensional chip
Xilinx Virtex-7 2000T FPGA chip
NVIDIA TESLA K20 GPU chip
World’s 2nd densest chip 6.8 Billion transistors
World’s densest chip 7.1 Billion transistors
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 31

Moore’s Law
We will continue with this discussion !
 An observation made by Gordon Moore holding true since 1965

One of the two founders of Intel
 Robert Noyce is the other founder
 Number of transistors on a chip doubles every two years

Because transistors are becoming smaller !
 We will continue to shrink size of transistors !
 We will continue to double the number of transistors
Transistors
are now
nano size
IBM Power 7
8 cores
1.2 Billion
transistors
3-D transistors
increase the transistor
density per chip
3-D chips increase
the transistor
density per chip
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 32

Analysis of the Term Project
 The term project black-box view
 The term project operation diagram
 The term project black box partitioning
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 33

The Analysis of the Term Project
 Polytechnic Playing Machine, Ppm

The term project is human vs. machine
 There are two other Ppm versions which are not term
projects


Machine vs. machine
Human vs. human
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 34

The Term Project, Ppm
 The black-box view
From the input devices
13
From page 2 of the Term Project Handout
19
Ppm
To the output devices
Figure 1. The Ppm black box view.

Ppm is sequential (not combinational)
 A large number of FFs are used !
 We need to partition the Ppm based on major operations
• We have to obtain the operation diagram
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 35
The Term Project, Ppm
 The black-box view

From page 3 of the Term Project Handout
SW7 - SW4 P1SEL
RD0
RD1
4
LD7 - LD4
RD2
RD3
3
SW3 - SW1 TRD
LD3
Add
STR0
STR1
SW0 P1add
LD2 - LD0
STR2
BTN3 P1play
BTN2 P2play
Ppm

CG
CF
CE
CD
CC
BTN1 Reset
CB
Four 7-Segment Displays
CA
A4
BTN0 Shpts
A3
CLK1 Clock
A1
A0
Figure 3. Inputs and outputs of the Ppm term project.
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 36

The term project, Ppm
 The input/output devices of the Ppm (without clock)

From page 2 of the Term Project Handout
All zero when the
FPGA is downloaded/reset
LED Lights
P1SEL
SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0
Position Displays
A display blinks fast if display overflow
All displays blink if points limit exceeded
STR
Random Digit
LD7
PD3 PD2 PD1 PD0
Add
RD
Switches
7-segment displays
Use SW3-SW0 as RD
P1add
LD6
LD5
BTN3
P1play/
NextRDs/
Code digits
LD4
LD3
LD2
LD1
LD0
BTN2
BTN1
BTN0
P2play
Reset
Shpts/
Code digits
Push buttons
Figure 2. FPGABoard Input/Output device utilization of the Ppm Term Project.
Please be gentle with push buttons and switches
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 37

Ppm Simplified Operation Diagram
Reset mode
Press BTN3 4 times
Player 1 mode
Press BTN3
after playing
RD with an
adjacency
Press BTN2 to skip
Press BTN2 after playing
RD without an adjacency
Player 2 mode
Press BTN2
after playing
RD with an
adjacency
Convert the simplified
operation diagram
to a (detailed)
operation diagram
Convert each circle to
one or more circles
(steps or states)
Press BTN3 after
playing RD without
an adjacency
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 38
Reset mode
(Initial state)
Player 1 presses BTN3, P1play, four times to play
Player 1 turns on SW0 if wanted. Player 1 turns on and off one
of SW7-SW4 to select a position. Player 1 turns off SW0 if on
2
Player 1 points being calculated !
3
If one of SW7-SW4 is on
in state 3, a random digit
is input for the machine
player from SW3-SW0
when BTN2 is pressed
Player 1 examines the s ituation !
Player 1 presses BTN3, P1play,
Player 1 presses BTN2, P2play,
to allow the machine player to play
to allow herself to play again if
there is an adjacency
4
Player 2 thinks !
r2
Playe
skips p
lay
Player 2 plays on a pos ition
5
Player 2 points being calculated !
6
Player 1 examines the situation !
Player 1 can press BTN3, Reset, in any
state to return to the Reset state, State 0
Player 1 presses BTN3, P1play,
to allow hers elf to play
Player 1 can press BTN4, Shpts, in any state to see players’ points
pr esse s
la y
P laye r 1 pla y, to skip p
, P2
2
N
T
B
From page 8 of the Term Project Handout
Player 1 can press BTN3, P1play,
in state 1 or 3 to see next two RDs
Player 1 press es BTN2, P2play,
to allow the machine player to
play again if there is an adjacency
Ppm
operation
diagram
The game is reset : 0 points for players, 0s on position displays !
Player 1 thinks !
Player 1 mode
(Player 1 plays)
Ppm
Input/output
relationship
0
1
Player 2 mode
(Player 2 plays)
LD0-LD2 on the
FPGA board
show the
current state
Download to the FPGA chip
Figure 5. The operation diagram of Ppm.
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 39
Reset mode
(Initial state)
Download to the FPGA chip
The game is reset : 0 points for players, 0s on position displays !
Player 1 presses BTN3, P1play, four times to play
1
Points Calculation block
Input/Output Block
Player 1 thinks !
Player 1 mode
(Player 1 plays)
Human play block
Player 1 can press BTN3, P1play,
in state 1 or 3 to see next two RDs
pr esse s
la y
P laye r 1 pla y, to skip p
, P2
2
N
T
B
Player 1 turns on SW0 if wanted. Player 1 turns on and off one
of SW7-SW4 to select a position. Player 1 turns off SW0 if on
2
Player 1 points being calculated !
3
If one of SW7-SW4 is on
in state 3, a random digit
is input for the machine
player from SW3-SW0
when BTN2 is pressed
Player 1 examines the s ituation !
Play check block
Player 1 presses BTN3, P1play,
Player 1 presses BTN2, P2play,
to allow the machine player to play
to allow herself to play again if
there is an adjacency
4
r2
Playe
skips p
lay
Player 2 plays on a pos ition
5
Player 2 points being calculated !
6
Player 1 examines the situation !
Player 1 can press BTN3, Reset, in any
state to return to the Reset state, State 0
Player 1 presses BTN3, P1play,
to allow hers elf to play
Player 1 press es BTN2, P2play,
to allow the machine player to
play again if there is an adjacency
Input/Output
Block is active
in every state
Player 2 thinks !
Player 2 mode
(Player 2 plays)
Machine Play
Block is also
active states
2 and 5
Player 1 can press BTN4, Shpts, in any state to see players’ points
Machine play block
0
Figure 5. The operation diagram of Ppm.
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 40

The Ppm Term Project Partitioning
 We have observed the following major operations






Interfacing to the input/output devices
Handling human player’s play
Controlling display operations based on game rules
Calculating new player points
Determining the machine player play
Hint for general partitioning
 If you cannot figure out major operations, partition
one major operation at a time
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 41
The Ppm Term Project Partitioning
 Any other major operation ?
Control (time) the operations
A Digital System
 All other operations
Reset mode
(Initial state)
Download to the FPGA chip
0
The game is reset : 0 points for players, 0s on position displays !
Player 1 can press BTN3, P1play,
in state 1 or 3 to see next two RDs
Player 1 presses BTN3, P1play, four times to play
Player 1 thinks !
pr esse s
la y
P laye r 1 pla y, to skip p
, P2
BTN 2
Player 1 turns on SW0 if wanted. Player 1 turns on and off one
of SW7-SW4 to select a position. Player 1 turns off SW0 if on
2
Player 1 points being calculated !
3
If one of SW7-SW4 is on
in state 3, a random digit
is input for the machine
player from SW3-SW0
when BTN2 is pressed
Player 1 examines the s ituation !
Player 1 presses BTN3, P1play,
Player 1 presses BTN2, P2play,
to allow the machine player to play
to allow herself to play again if
there is an adjacency
4
r2
Playe
skips p
lay
Player 2 plays on a pos ition
5
Player 2 points being calculated !
6
Player 1 examines the situation !
Player 1 can press BTN3, Reset, in any
state to return to the Reset state, State 0
Player 1 presses BTN3, P1play,
to allow hers elf to play
Player 1 press es BTN2, P2play,
to allow the machine player to
play again if there is an adjacency
Player 2 thinks !
Player 1 can press BTN4, Shpts, in any state to see players’ points
1
Player 1 mode
(Player 1 plays)

Player 2 mode
(Player 2 plays)

Figure 5. The operation diagram of Ppm.
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 42

Digital Systems
 A digital system consists of digital circuits

A digital system performs microoperations
 A microprocessor is a digital system
 An iPhone is a digital system
 A computer is a collection of digital systems
MIPS R10000 die
Intel Tukwila die
Sun Niagara die
IBM Power 6 die
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 43

Digital Systems
 This first partitioning of a digital system is universal

A data unit (datapath)
 It performs microoperations

A control unit
 It controls the datapath
Other digital systems/
Input/Output devices
Registers
ALUs
buses
control signals
status signals
Sequencer
Data Unit
(Datapath)
Control Unit
Figure 7. A large scale view of a digital system.
From page 10 of the Term Project Handout
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 44

Digital Systems
 The data unit has registers, ALUs and buses
to perform microoperations

Registers keep (store) data (operands and results)
 Registers are implemented by using FFs

Arithmetic Logic Units (ALUs) perform additions,
subtractions, multiplications, ANDS, ORs, etc.
 ALUs are implemented by using gates

Buses interconnect registers and ALUs
 Buses are implemented by using gates to control the bus
lines (wires) and if necessary FFs
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 45

Digital Systems
 The data unit is highly regular

Pieces of hardware repeated many times
 1-bit MUX repeated 32 times for a 32-bit MUX
 4-bit ADDer repeated 8 times for a 32-bit ADDer
 It is easier to design, test, modify,
manufacture, upgrade, service, maintain
regular hardware
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 46

Digital Systems
 The control unit determines the sequence of
microoperations based on status signals

The control unit goes through steps (states)
 In each state, it enables the microoperations of that
state to happen in the data unit based on the status
signals
• Microoperations must start at the right time with correct
inputs and end at the right time with correct outputs
• Glitches, gate delays must be accounted for
 The control unit is not regular
 The control unit also contains many gates and flip-flops
• The control unit has a large amount of random logic
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 47

The Ppm Term Project
 Ppm is a digital system !
From the input devices
19
13
Ppm
To the output devices
Figure 1. The Ppm black box view.
 The Ppm term project partitioning

First partitioning of the digital system
 Control Unit
 Data Unit

core
Second partitioning (Data Unit partitioning)





Interfacing to the input/output devices core
Handling human player’s play core
Controlling display operations based on game rules core
Calculating new player points core
Determining the machine player play non-core
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 48

The Ppm Digital System Partitioning
From page 9 of the Term Project Handout
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 49

The term project black box partitioning
• Six schematics for six blocks
•
•
Block 1 : Control Unit
Block 2 : Input/Output
• Experiment 1 is on a circuit in this block
•
•
•
•
Block 3 : Human Play
Block 4 : Play Check
Block 5 : Points Calculation file
Block 6 : Machine
• The Machine Play Block uses all other blocks except the
Human Play Block
• These six schematics are in the ppm.sch file
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 50

Play Check Block, Block 4
From page 22 of the Term Project Handout
 The block-box view
From page 9 of the Term Project Handout
36
Block 4
63
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 51

Play Check Block, Block 4
 Has 36 inputs and 63 outputs

Both players share Block 4
 Has sequential circuits to

Keep position displays
 Performs operations on them



Keep players’ points
Generate random digits
Generate the code digits
 Has circuits to add displays and the random digit

Today : Adding Position Display 3 and RD
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 52

The Ppm Data Unit
 Block 4, Play Check Block
36
Block 4
63
 It has three major operations

Storing the displays, player points and random digit
 Position Displays, Points Storage and Random Digit Generation
Subblock

Handling display manipulations
 Display Add and Compare Subblock
• Also, generate the code digits and calculate the code reward

Determining digit played
 Played Digit Determination (BRWD) Subblock
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 53

Play Check Block, Block 4
Today : 4-bit
ADDer circuit
 The partitioning
2
1
3
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 54

Play Check Block, Block 4
Position
Displays,
Points
Storage &
Random
Digit
Generation
Subblock
1
2
Display
Add
And
Compare
Subblock
Today :
4-bit
ADDer
circuit
Played Digit
Determination
Subblock
3
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 55

Play Check Block, Block 4
 The Position Displays, Points Storage and Random Digit
Generation Subblock partitioning
Registers
P1PT
Counter
R2D
R1D
1
3
1
2
DISP
0
P2PT
Highly regular hardware
RD
MUX
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 56

2
Play Check Block, Block 4
 Display Add and Compare Subblock partitioning
Code
reward
points
Today’s work :
4-bit ADDer
Pd3prd
NPDISP15-NPDISP12
Highly
regular
hardware
Pieces of
hardware
duplicated
several
times
Pd0prd
4-bit ADDers repeated four times
NPDISP3-NPDISP0
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 57

Play Check Block, Block 4
 Played Digit Determination Subblock Partitioning
MUXes
3
ENCPSEL
PSEL
Pdprd
NPSELDISP
BRWD
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 58

Machine Playing Strategies
 Teams have to come up with a primary playing
strategy before they can design their machine player

A playing strategy is shown as a graph and consists of
 Conditions shown as ovals
• Game situations
 Actions shown as rectangles
• Playing the random digit on a display
• Skipping the plays

The graph is NOT with respect to time
 The graph is with respect to game situations !
 Teams must also have to come up with a secondary
strategy to resolve game situations where the
primary playing strategy results in multiple playable
positions
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 59

Course web site machine player
 Its primary strategy considers now and near future

Six different actions
 Goes for the most regular reward points : Action 0
• When it is ahead or behind
 Goes for the most adjacencies : Action 1
• When it is ahead
 Goes for a zero display : Action 2
• When it is the beginning of the game
 Goes for the largest display : Action 3
• When it is ahead or behind
 Goes for a code digit : Action 4
• When it is ahead or behind
 Skips the play when it is ahead : Action 5

Its secondary strategy is always play on the rightmost of
playable positions and direct playing
 Except for Action 4 which the leftmost and with an addition
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 60
Course web site machine player playing strategy
Player 2 wins
the game with
regular reward
Player 2 cannot win the
game with regular reward
Action 0
Player 2
is behind
Action 4
Action 1
Action 2
Adjacency
Action 1
Action 3
Action 5
From page 42 of the Term Project Handout

Action 0
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 61

Course web site machine player
Decision making
Information gathering
Sequencing
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 62

A Machine Player Strategy
Play on the
(rightmost)
largest
regular
reward
position
(directly if
equal)
(Action 0)
RD : 3
Displays : C3F8
Displays : F3F8
 There is just one action and no condition

The primary strategy is playing on the rightmost largest
regular reward position
 No checking for code digits

The secondary strategy is playing
 On the rightmost of equally playable largest regular reward
positions
 Directly if playing directly and with an addition give the regular
reward points
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 63

A Machine Player Strategy
 Playing Strategy of Player 1 of Ppmmvsm
Play on the
(rightmost)
largest
regular
reward
position
(directly if
equal)
(Action 0)
448C
4
 44CC
E233
1
 F233
FDDF
2
 FDFF
0000
0
 0000
 There is just one action and no condition

The primary strategy is playing on the largest regular
reward position
 No checking for code digits !

The secondary strategy is playing on the rightmost of
equally playable (largest regular reward) position directly
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 64

Playing Strategy of Player 1 of Ppmmvsm
 Its Implementation
Play on the
(rightmost)
largest
regular
reward
position
(directly if
equal)
(Action 0)
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 65

Common Logic Errors
 Discovering logic errors by means of simulations
The correct expression
Must be
corrected
a
Input “a” is input “b”
by mistake !
y(a, b, c) = a.b + a.c
b
b
c
y(a, b, c) = a.b.(b.c)
U3
Must be corrected
The OR gate is an AND gate by mistake !
The incorrect
expression
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 66

Common Logic Errors
 Discovering logic errors by means of simulations
U1
U2
U2 has no Load
Must be
U2 output is not used corrected
a
Must be
corrected
U4 input has no driver
U4 input is not
connected to an output.
Its input value is Hi-Z
(High-Impedance) as
there is infinite
impedance (resistance)
into the U4 input so no
current can flow in
U4
b
y
a
c
U3
Must be corrected
Multiple drivers on output y
U3 and U4 outputs are short circuited
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 67

Assignment by next lab
 Make sure that you have completed Experiment 1 and
Experiment 2



Your experiment will be collected and graded
The last day to submit Experiment 1 as a team is March 7,
2014
The last day to submit Experiment 2 as a team is March 7,
2014
 It will be graded and returned by the following lab
Submit your Experiment 1 during a lab session !
Not during Open Lab Hours !
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 68
Make sure you have the LABS account and see the S drive
Make sure you have installed WebPACK 12.4 on your laptop
Make sure you create a CS2204 folder on both
Read slides at the end to learn about the software, Project Manager,
Schematic design and other related topics
Do not leave the lab before your partners finish
► Help your partners
QUESTIONS ?
Continue
reading the
Term
Project
handout
Digital
Logic
and
State Machine Design
Think about
the machine
player
strategy
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 69

Today’s Individual Xilinx Work
 We will continue to study (analyze) the term project

We will continue with the 4-bit 2-to-1 MUX in Block 3 : Experiment 1
 We will test our design on the computer assuming real gates
•
Do timing simulations
 We will decide whose project will be submitted and submit the project

We will use our knowledge of 1-bit ADDers to modify a portion of a term
project to develop a 4-bit ADDer in the Play Check Block (Block 4) :
Experiment 2
 The 1-bit ADDer expression is the same as the one obtained in class
•
•
We will draw a 1-bit ADDer
We will use a Xilinx 4-bit ADDer as a 3-bit Adder
•
Do logic simulations
•
To create the bit file
•
Do timing simulations
 We will do a schematic check
 We will test our design on the computer
 We will do a Xilinx IMPLEMENTATION of the project
 We will test our 4-bit ADDer design on the computer assuming real gates
► We will see the addition delay due to gate delays
► We will see the glitch due to gate delays
 We will test our design on the FPGA board
•
•
We will program the FPGA chip ≡ download the bit file
We will use switches and a LED light to test our design on the FPGA board
 Help our partners complete today’s project
 We will continue reading the Term Project handout

Also read slides at the end to learn about the software, Project Manager,
Schematic design and other related topics
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 70

1.
Today’s Individual Xilinx Lab Work
Open the ppm project in the exp1 folder
Make sure the team info is placed on all the schematics !
Make sure the Xilinx IMPLEMENTATION is already done
Perform functional simulations on the 4-bit MUX in Block 3 of the term
project to refresh your memory
Make sure the Experiment 1 circuit is completed
2.
Submit the Experiment 1 project after deciding whose project is
the best to submit
By using Microsoft and Xilinx ISE create the exp2 from the exp1
Open the ppm project in the exp2 folder and analyze the project
manager window
Open the schematics and analyze them
3.
4.
5.

6.
7.
8.
9.

We will experiment with the Ppm schematics
Make sure the team info is placed on all the schematics
Study the 4-bit ADDer schematic in the Play Check Block in
schematic 4 (ppm4.sch) of the term project to refresh your
memory on the ADDer
Replace the 4-bit ADDer in Block 4 with our own circuits in Block 3
of the term project by using circuits shown on pages 3 and 4 of
Handout 3
Do a schematic check on the new design
Perform functional simulations on the 4-bit Adder
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 71

10.
11.
12.
Today’s Individual Xilinx Lab Work
Perform a Xilinx IMPLEMENTATION
Perform timing simulations on the 4-bit ADDer
Download the Ppm project to the FPGA chip and play the
game and to verify that the schematic works correctly
Program the FPGA chip



13.
14.
Test the Ppm to see if it is working
•
Play the game on the FPGA board
If it does not work, inspect your circuit in Block 3 and correct the
circuit
Help your partners complete today’s project
Submit your exp2 project once everyone completes the
design
Continue reading the Term Project handout
15.
Study and play the other two types of the Ppm game to think
more about the our machine player’s strategy




Human vs. human : ppmhvsh
Machine vs. machine : ppmmvsm
•
Think about the playing strategy of the machine player that will be designed
Also read slides at the end to learn about the software, Project
Manager, Schematic design and other related topics
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 72

Today’s Individual Xilinx Lab Work
1.
Open the ppm project in the exp1 folder
a) Start Xilinx ISE and then open the Ppm project in the
exp1 folder

Check that the Xilinx IMPLEMENTATION has been done
•
If the IMPLEMENTATION has not been done do it later
b) Look at the six Ppm schematics

Remember that we must create a new project from an earlier one by
using Microsoft and Xilinx ISE in the lab
c) Enter the team information to all the schematics if it has
not been entered

Save the schematics if the team information is entered
d) Perform functional simulations on the 4-bit MUX in Block 3
of the term project to refresh your memory

Make sure you save the schematics if you changed them then
perform a synthesis before you start the simulation
e) Make sure the Experiment 1 circuit is completed

The last Xilinx IMPLEMENTATION is done with correct
number of warnings and utilization
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 73

Today’s Individual Xilinx Lab Work
1.
Open the ppm project in the exp1 folder
e)
Make sure the Experiment 1 circuit is completed

That is on screen you have the following :
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 74

Today’s Individual Xilinx Lab Work
1.
Open the ppm project in the exp1 folder
e)
Make sure the Experiment 1 circuit is completed

If it is not complete finish the design by studying Lab 4
presentation for Experiment 1
•
So that eventually Block 3 looks like as follows :
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 75
Today’s Individual Xilinx Lab Work

1.
Open the ppm project in the exp1 folder
e)
Make sure the Experiment 1 circuit is completed

If it is not complete finish the design by studying Lab 4 presentation
for Experiment 1 so that the new circuit looks like as follows :
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 76

Today’s Individual Xilinx Lab Work
2.
Submit the Experiment 1 project after deciding
whose project is the best to submit

Decide whose project on the team will be submitted

Block 3 must look like as follows :
Experiment 1
Make sure your circuits
follow the Term Project
Check List handout
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 77

Today’s Individual Xilinx Lab Work
2.
Submit the Experiment 1 project after deciding whose
project is the best to submit

Fill out a Term Project Check List handout before signaling to the
TA

Block 3 must look like as follows :
Experiment 1
Make sure your circuits
follow the Term Project
Check List handout
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 78

Today’s Individual Xilinx Lab Work
3.
By using Microsoft and Xilinx ISE create the exp2 from the
exp1

4.
Remember that we must create a new project from an earlier one
by using Microsoft and Xilinx ISE in the lab
Open the ppm project in the exp2 folder and analyze the
project manager window
5. Open the schematics and analyze them

Take a look at the six schematics for the six blocks of the
term project
•
•
•
•
•
•

Block
Block
Block
Block
Block
Block
1 : Control Unit
2 : Input/Output
3 : Human Play
4 : Play Check
5 : Points Calculation
6 : Machine Play
These six schematics are in the ppm.sch file
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 79

Today’s Individual Xilinx Lab Work
5. Open the schematics and analyze them

Enter team information on the schematics if it is not shown
•
•
•
•
•
•
•
•
To enter the team info on schematic 1 switch to schematic 1 and zoom
into the lower right corner where project information is shown :
Right click on the project information object
Select Object Properties
In the Name area enter the names of the members of the team
In the Title area enter “
CS 2204 – Your Lab Section – Spring 2014”
• Place some space before “CS 2204” so that it is not right next to
“Ppm Control Unit”
Save the schematic
Do these for the other five schematics
Zoom into the lower right corner of each schematic and verify that the
info is correct
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 80

Today’s Individual Xilinx Lab Work
5.
Open the schematics and analyze them
•
Enter team information on the schematics if it is not shown
•
All project schematics must carry info about the company, designers
and dates of creation and alteration on the lower right side
The CS2204
team
information
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 81

Today’s Individual Xilinx Lab Work
5.
Open the schematics and analyze them
•
Enter team information on the schematics if it is not shown
•
Enter team information on all schematics, the same way : Manually !
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 82

Today’s Individual Xilinx Lab Work
6. Study the 4-bit ADDer schematic in the
Play Check Block in schematic 4 of the term
project to refresh your memory on the
ADDer



Switch to schematic 4
Zoom into the middle right area, containing the
Adding RD to the Displays Subsubblock
There is a Xilinx macro (a Xilinx Design Block,
XDB)

A 4-bit ADDer, ADD4 : U150
•
•

It adds two 4-bit numbers
It adds the leftmost display and the random digit
 It also generates the overflow signal of the display
See the schematic on the next slide
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 83
Today’s Individual Xilinx Lab Work


Ppm Schematic 4
Xilinx
4-bit
ADDer
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 84

Today’s Individual Xilinx Lab Work
6.
Study the 4-bit ADDer schematic in the Play Check Block in
schematic 4 of the term project to refresh your memory on
the ADDer

The ADDer is in the Adding RD to the Displays Subsubblock
PD3
RD
PD3 + RD
Leftmost display + random digit
Display 3 overflow
NPDISP [15 – 12]
Pd3prd
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 85

Today’s Individual Xilinx Lab Work
6. Study the 4-bit ADDer schematic in the Play Check
Block in schematic 4 of the term project to refresh
your memory on the ADDer


The ADDer is in the Adding RD to the Displays
Subsubblock
Search for the inputs and outputs of the ADDer by
clicking on the Query button on the left side of the
schematic sheet
In the Nets mode of the Query window that will pop up
Determine which components generate the inputs
 DISP15, DISP14, DISP13, DISP12, RD3, RD2, RD1, RD0
Determine which components use outputs
 NPDISP15, NPDISP14, NPDISP13, NPDISP12, Pd3prd
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 86

Today’s Individual Xilinx Lab Work
6. Study the 4-bit ADDer schematic in the Play Check
Block in schematic 4 of the term project to refresh
your memory on the ADDer

How can I search for a wire in the
schematics ?
 To search for wires press Ctrl+Q to have the
Query window
 Select the Nets mode
 Click on the input wire, such as DISP15
 The software will automatically switch to the
first schematic that has the wire and show
the wire in yellow
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 87

Today’s Individual Xilinx Lab Work
6. Study the 4-bit ADDer schematic in the Play Check
Block in schematic 4 of the term project to refresh
your memory on the ADDer

How can I search for a wire in the
schematics ?
 To search for wires press Ctrl+Q to have the
Query window
 There may be more than one schematic using
the wire, in that case you can determine all
the schematics and how they use the wire by
expanding Sheets in the Highlight window and
then double clicking on each sheet
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 88

Today’s Individual Xilinx Lab Work
6.
Study the 4-bit ADDer schematic in the Play Check Block in
schematic 4 of the term project to refresh your memory on
the ADDer

Xilinx 4-bit ADDer : ADD4

It is used for Unsigned Binary and 2’s Complement Binary additions
•
•
For Unsigned binary additions, CO indicates the overflow
For 2’s Complement additions, OFL indicates the overflow
Xilinx 4-bit ADDer operation table
Situation
A + B + CI = K ≤ 15
A + B + CI = K > 15
Operation
S ≤ 15 ; CO = 0
S = K - 16 ; CO = 1
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 89

Today’s Individual Xilinx Lab Work
6. Study the 4-bit ADDer schematic in the
Play Check Block in schematic 4 of the term
project to refresh your memory on the
ADDer

Observe the internal structure of the Xilinx 4bit ADDer and compare it with the gate
networks on page 4 of Handout 3

Do a Hierarchy Push and see that it is implemented by
Xilinx differently from the one discussed in class
•
•
It does not have four cascaded Full Adders !
See internal implementation of the 4-bit Xilinx ADDer on
the next slide
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 90
Today’s Individual Xilinx Lab Work


Xilinx 4-bit ADDer is not implemented by 1-bit ADDers
Xilinx 4-bit ADDer operation table
Situation
Operation
A + B + CI = K ≤ 15
S ≤ 15 ; CO = 0
A + B + CI = K > 15
S = K - 16 ; CO = 1
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 91

Today’s Individual Xilinx Lab Work
6.
Study the 4-bit ADDer schematic in the Play Check Block in
schematic 4 of the term project to refresh your memory on
the ADDer


Close the schematic of the internal circuit of the Xilinx 4-bit
ADDer
Perform functional simulations on the 4-bit Adder

Select the wires as follows :
•
•
•
RD3, RD2, RD1, RD0
DISP15, DISP14, DISP13, DISP12
NPDISP15, NPDISP14, NPDISP13, NPDISP12
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 92

Today’s Individual Xilinx Lab Work
6.
Study the 4-bit ADDer schematic in the Play Check Block in schematic 4 of
the term project to refresh your memory on the ADDer

Perform functional simulations on the 4-bit Adder
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 93

Today’s Individual Xilinx Lab Work
7. Replace the 4-bit ADDer in Block 4 with our
own circuits in Block 3 of the term project
by using circuits shown on pages 3 and 4 of
Handout 3

Delete the Xilinx 4-bit ADDer in schematic 4


Do not delete the wires
Save schematics
•
See modified ppm4.sch on the next slide
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 94
Today’s Individual Xilinx Lab Work


Ppm Schematic 4
Xilinx
4-bit ADDer
deleted
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 95

Today’s Individual Xilinx Lab Work
7. Replace the 4-bit ADDer in Block 4 with our own
circuits in Block 3 of the term project by using
circuits shown on pages 3 and 4 of Handout 3

We will implement the 4-bit ADDer by using one 1-bit
ADDer and one 3-bit ADDer

We will do this to save space in Block 3
•
•
Four 1-bit ADDers would occupy a large space, leaving little
space for the remaining experiments
The one 1-bit ADDer will generate
 The leftmost NPDISP output : NPDISP15
 Pd3prd, C4
•
The 3-bit ADDer will generate
 The rightmost two NPDISP outputs : NPDISP14, NPDISP13,
NPDISP12
 C3
•
Xilinx does not have 3-bit ADDers
 We will use a Xilinx 4-bit ADDer as a 3-bit ADDer
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 96

Today’s Individual Xilinx Lab Work
7. Replace the 4-bit ADDer in Block 4 with our own
circuits in Block 3 of the term project by using
circuits shown on pages 3 and 4 of Handout 3

We will implement the 4-bit ADDer by using one 1-bit
ADDer and one 3-bit ADDer
DISP15
RD3
DISP14
DISP13
DISP12
RD2
RD1
RD0
C4
Cout
Pd3prd
Full ADDer
0
3-bit ADDer
C3
Cin
C0
NPDISP15
NPDISP14
NPDISP13
NPDISP12
Look at pages 3 and 4 of Handout 3
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 97

Today’s Individual Xilinx Lab Work
7. Replace the 4-bit ADDer in Block 4 with our own
circuits in Block 3 of the term project by using
circuits shown on pages 3 and 4 of Handout 3


Switch to the Human Play Block, Block 3 or ppm3.sch
Draw the schematic of the 4-bit ADDer by using
Handout 3 on the lower side in schematic 3

First draw a 1-bit Adder (leftmost Full Adder) to add the
most significant inputs by using page 4 of Handout 3
•
See the correspondence between the Handout 3 circuit and
the circuit on the previous slide
 Add DISP15 and RD3 and C3 (from the right stage)
 To generate NPDISP15 and a Pd3prd
Pd3prd
DISP15 a
RD3 b
C3 c
cout(a, b, c)
FA
sum(a, b, c)
NDISP15
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 98

Today’s Individual Xilinx Lab Work
7.
Replace the 4-bit ADDer in Block 4 with our own circuits in Block 3 of the
term project by using circuits shown on pages 3 and 4 of Handout 3

Draw the schematic of the 4-bit ADDer by using Handout 3 on the lower side in
schematic 3

First draw a 1-bit Adder (Full Adder) to add the most significant inputs by using page 4 of
Handout 3
Pd3prd
DISP15 a
cout(a, b, c)
RD3 b
FA
C3 c
sum(a, b, c)
NDISP15
DISP15
RD3
C3
Pd3prd
NPDISP15
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
CS 2204 Spring 2014Experiment 1-2 Lab 5 Page 99
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Today’s Individual Xilinx Lab Work
7. Replace the 4-bit ADDer in Block 4 with our own
circuits in Block 3 of the term project by using
circuits shown on pages 3 and 4 of Handout 3

Determine which output is “cout” and which output is the
“sum” output
•
The S3 output is Sum(a, b, c) in Handout 3
 S3 generates NPDISP15
•
The CO output is cout(a, b, c) in Handout 3
 CO generates Pd3prd
S3 = Sum(a, b, c) = a b c + a b c + a b c + abc
CO = cout(a, b, c) = bc + ab + ac
a = DISP15
b = RD3
c = C3
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 100
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Today’s Individual Xilinx Lab Work
7. Replace the 4-bit ADDer in Block 4 with our own
circuits in Block 3 of the term project by using
circuits shown on pages 3 and 4 of Handout 3

See the correspondence between the Handout 3 circuit
inputs and outputs and Xilinx Adder inputs and outputs

Determine which output is “cout” and which output is the “sum”
output

The expressions for this 1-bit ADDer are as follows then
NPDISP15 = DISP15 RD3 C3 + DISP15 RD3 C3 + DISP15 RD3 C3 + DISP15 RD3 C3
Pd3prd = cout(a, b, c) = RD3 C3 + DISP15 RD3 + DISP15 C3
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 101
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Today’s Individual Xilinx Lab Work
7. Replace the 4-bit ADDer in Block 4 with our own
circuits in Block 3 of the term project by using
circuits shown on pages 3 and 4 of Handout 3


Switch to the Human Play Block, Block 3 or ppm3.sch
Draw the schematic of the 4-bit ADDer by using Handout
3 on the lower side in schematic 3

First draw a 1-bit Adder (Full Adder) to add the most
significant inputs by using page 4 of Handout 3
•
•
You will implement the sum and cout outputs by using 2-level
AND-OR gate networks on page 4 of Handout 3
In or order to save space we will not use inverters
 The NPDISP15 (sum) expression requires inverters supplying
complemented inputs to AND gates
 We will use 3-input AND gates whose two inputs are internally
inverted : AND3B2
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 102

Today’s Individual Xilinx Lab Work
7. Replace the 4-bit ADDer in Block 4 with our own
circuits in Block 3 of the term project by using
circuits shown on pages 3 and 4 of Handout 3

Draw the schematic of the 4-bit ADDer by using Handout
3 on the lower side in schematic 3

First draw a 1-bit Adder (Full Adder) to add the most
significant inputs by using page 4 of Handout 3
•
•
•
•
You will use the Symbols button on the leftmost side (or
Ctril+M) to get the component list
You will use the Add wire button on the leftmost side (or
Ctrl+W) to draw wires
To rotate components right press ctrl-r
Note, wires cannot be rotated
 But, by pulling from one end of a wire, it can be rotated !
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 103
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Today’s Individual Xilinx Lab Work
7. Replace the 4-bit ADDer in Block 4 with our own
circuits in Block 3 of the term project by using
circuits shown on pages 3 and 4 of Handout 3


Label the wires (inputs and outputs) based on your analysis
in part (6)
Label the components starting at U279


Determine that there is no component labeled U279 and
above
How can I search for a component in the schematics, for
example, to search for component U278 ?
•
•
•
•
•



To search for components press Ctrl+F to find the component
with a label
Select the Instance mode
Select With Name
Enter U278 and then press Enter
The Xilinx software will show the Xilinx 2-input OR gate OR2 in
a yellow rectangle in Block 3
The last component label for the 1-bit adder is U287
Save the schematic
See modified Block 3 on next three slides
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 104
Today’s Individual Xilinx Lab Work


Modified Block 3
NPDISP15
sum
1-bit ADDer
Pd3prd
cout
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 105
Today’s Individual Xilinx Lab Work


Modified Block 3
NPDISP15
sum
CS 2204 Spring 2014Experiment 1-2 Lab 5 Page 106
Today’s Individual Xilinx Lab Work


The modified ppm3.sch
Pd3prd
cout
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 107
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Today’s Individual Xilinx Lab Work
7.
Replace the 4-bit ADDer in Block 4 with our own circuits in
Block 3 of the term project by using circuits shown on pages
3 and 4 of Handout 3

Perform functional simulations on the Full Adder


Use the truth table on page 4 of Handout 3 or slide 99
Make sure the circuit is beautified and the schematic is saved again

Note that to do functional simulations, you must perform a
synthesis
You will see that there are 142 warnings, many of them new due
to copying this project from exp1
ReRun the synthesis so that you eliminate most of the new
warnings
There will be 68 warnings after the second synthesis
Note that in Experiment 1 we had 64 warnings after the second
synthesis
One warning that we had in Experiment 1 is eliminated : The OFL
output of the ADDer we deleted is no longer a warning
The five new warnings are for XLXN_11261, NPDISP14,
NPDISP13, NPDISP12 and C3
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 108
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Today’s Individual Xilinx Lab Work
7.
Replace the 4-bit ADDer in Block 4 with our own circuits in
Block 3 of the term project by using circuits shown on pages
3 and 4 of Handout 3

Perform functional simulations on the Full Adder


Use the truth table on page 4 of Handout 3 or slide 99
Make sure the circuit is beautified and the schematic is saved again

Note that to do functional simulations, you must perform a
synthesis
There will be 68 warnings after the second synthesis
The four new warnings are for XLXN_11261, NPDISP14,
NPDISP13 and NPDISP12
Search for XLXN_11261 and confirm that it is the wire
connected to the CI input of the ADDer we deleted (U150) and
can be ignored
NPDISP14, NPDISP13 and NPDISP12 are the remaining outputs
of the ADDer we deleted and have not been implemented yet and
can be ignored
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 109
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Today’s Individual Xilinx Lab Work
7. Replace the 4-bit ADDer in Block 4 with our own
circuits in Block 3 of the term project by using
circuits shown on pages 3 and 4 of Handout 3

Perform functional simulations on the Full Adder

Use the truth table on page 4 of Handout 3 or slide 99
Make sure you select the signals as follows :
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 110

Today’s Individual Xilinx Lab Work
7. Replace the 4-bit ADDer in Block 4 with our own
circuits in Block 3 of the term project by using
circuits shown on pages 3 and 4 of Handout 3

Perform functional simulations on the Full Adder


Use the truth table on page 4 of Handout 3 or slide 99
Make sure the circuit is beautified and the schematic is
saved again

Apply all eight input combinations to have all eight rows
of the truth table tried
Change your simulation duration to 5 ps so that you can
try all eight combinations in the window

See the next slide
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 111

Today’s Individual Xilinx Lab Work
7.
Replace the 4-bit ADDer in Block 4 with our own circuits in Block 3 of the
term project by using circuits shown on pages 3 and 4 of Handout 3

Perform functional simulations on the Full Adder
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 112

Today’s Individual Xilinx Lab Work
7.
Replace the 4-bit ADDer in Block 4 with our own circuits in
Block 3 of the term project by using circuits shown on pages
3 and 4 of Handout 3

Draw the schematic of the 4-bit ADDer by using Handout 3 on
the lower side in schematic 3

Draw the 3-bit Adder
•
We will use a Xilinx 4-bit ADDer (ADD4) as a 3-bit ADDer
 Add (DISP14, DISP13, DISP12) and (RD2, RD1, RD0) and Cin (always 0)
 To generate NPDISP14, NPDISP13, NPDISP12 and C3
DISP14
DISP13
DISP12
RD2
RD1
0
3-bit ADDer
C3
NPDISP14
NPDISP13
RD0
Cin
NPDISP12
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 113
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Today’s Individual Xilinx Lab Work
7.
Replace the 4-bit ADDer in Block 4 with our own circuits in
Block 3 of the term project by using circuits shown on pages
3 and 4 of Handout 3

Draw the 2-bit Adder

We will use a Xilinx 4-bit ADDer (ADD4) as a 2-bit ADDer
•
We have to connect 0 values to the unneeded inputs of the 4-bit Adder
so that the software package generates the bit file correctly
0
DISP14
B3
B2
C0
OFL
DISP13
B1
DISP12
0
RD2
B0
A3
A2
RD1
RD0
A1
A0
Xilinx 4-bit ADDer : ADD4
S3
S2
S1
S0
C3
NPDISP14
NPDISP13
NPDISP12
0
CI
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 114

Today’s Individual Xilinx Lab Work
7. Replace the 4-bit ADDer in Block 4 with our own
circuits in Block 3 of the term project by using
circuits shown on pages 3 and 4 of Handout 3

Draw the schematic of the 4-bit ADDer by using Handout
3 on the lower side in schematic 3

Draw the 3-bit Adder
•
We will use a Xilinx 4-bit ADDer (ADD4) as a 3-bit ADDer
 To rotate components right press ctrl-r
•
•

Make sure the circuit is beautified and the schematic is
saved


Label the wires (inputs and outputs) based on the previous slide
Label the Xilinx 4-bit ADDer (ADD4) as U288
Make sure the circuits in Block 3 follow the Term Project
Check List handout
See modified Block 3 on next two slides
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 115
Today’s Individual Xilinx Lab Work


The modified ppm3.sch
Make sure your circuits in
Block 3 follow the Term
Project Check List handout
3-bit ADDer
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 116
Today’s Individual Xilinx Lab Work


The modified ppm3.sch
DISP14
RD2
RD1
DISP13
RD0
DISP12
3-bit ADDer
implemented by
a 4-bit ADDer
NPDISP12
NPDISP13
C3
NPDISP14
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 117

Today’s Individual Xilinx Lab Work
7.
Replace the 4-bit ADDer in Block 4 with our own circuits in
Block 3 of the term project by using circuits shown on pages
3 and 4 of Handout 3

Perform functional simulations on the 3-bit Adder
• The adder has 6 inputs



Therefore, it is impractical to apply all possible 64 input
combinations
We will try to apply as many different input combinations as we
can
Note that to do functional simulations, you must perform a
synthesis
There will be 66 warnings after the synthesis
We added two new warnings due to the unused CO and OFL
output of the new ADDer we used
Four warnings that we had for the full adder are eliminated :
NPDISP14, NPDISP13, NPDISP12 and C2
We still have the XLXN_11261 warning
These 66 warnings are OK and we can proceed with functional
simulations
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 118

Today’s Individual Xilinx Lab Work
7. Replace the 4-bit ADDer in Block 4 with our own
circuits in Block 3 of the term project by using
circuits shown on pages 3 and 4 of Handout 3

Perform functional simulations on the 3-bit Adder
•
The adder has 6 inputs and 4 outputs
Make sure you select the signals as follows :
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 119

Today’s Individual Xilinx Lab Work
7. Replace the 4-bit ADDer in Block 4 with our own
circuits in Block 3 of the term project by using
circuits shown on pages 3 and 4 of Handout 3

Perform functional simulations on the 3-bit Adder
•
The adder has 6 inputs and 4 outputs



Therefore, it is impractical to apply all possible 64 input
combinations
We will try to apply as many different input combinations as we
can
See the next slide
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 120

Today’s Individual Xilinx Lab Work
7.
Replace the 4-bit ADDer in Block 4 with our own circuits in Block 3 of the
term project by using circuits shown on pages 3 and 4 of Handout 3

Perform functional simulations on the 3-bit Adder
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 121
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Today’s Individual Xilinx Lab Work
8.
Do a schematic check on the new design
 The schematic check is to see if there
are simple errors to catch on all
schematics

Select Tools  Check Schematic
• The Console panel will indicate that there
are no errors but two warnings
 See the next slide
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 122

Today’s Individual Xilinx Lab Work
8.
Do a schematic check on the new design
 The schematic check is to see if there are simple errors
to catch on all schematics
 Read the bottom portion of the Console panel for warnings and
correct them if there are any

The warnings are about
•
•
•


The unused wire attached to GND in Block 2 where GND was supplying the
Enable input to the deleted MUX, XLXN_88
An unused (unconnected) output in Block 4, RDC0
The unused wire attached to GND in Block 4 where GND was supplying the
CI input to the deleted ADD4 component, XLXN_11261
The three warnings are OK since we do not need these outputs
We will ignore these unneeded output warnings and decide there is
nothing to correct
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 123

Today’s Individual Xilinx Lab Work
8. Do a schematic check on the new design
The schematic check is to see if there are simple errors
to catch on all schematics



You might wonder how the project works if wires are not connected to
outputs nor inputs
• The Xilinx software integrates all the schematics during its
implementation
• If the wire names are the same, it would not matter where the
wires are placed, the software connects them internally
Schematic checks do not catch all the errors
 That is why after the Schematic checks we have to
perform
 Functional simulations
 Xilinx IMPLEMENTATIONs
 Timing simulations
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 124

Today’s Individual Xilinx Lab Work
9. Perform functional simulations on the 4-bit Adder
•
The adder has 8 inputs and 5 outputs
Make sure you select the signals as follows :
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 125

Today’s Individual Xilinx Lab Work
9. Perform functional simulations on the 4-bit
Adder


Apply as many different input combinations as
you can
See the next slide
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 126

Today’s Individual Xilinx Lab Work
9. Perform functional simulations on the 4-bit Adder
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 127

Today’s Individual Xilinx Lab Work
10. Perform a Xilinx IMPLEMENTATION
•
Xilinx IMPLEMENTATION is required after a schematic is
changed
•
•
•
When we indicate IMPLEMENTATION we mean Synthesis,
Implement Design and Generate Programming File steps we see
on the Project Navigator window
Since we changed schematics 3 and 4 we have to do a Xilinx
IMPLEMENTATION
Xilinx IMPLEMENTATIONS are needed for three reasons



Catching more errors not discovered via schematic checks and
functional simulations as the software analyzes the schematics
Catching even more errors by doing timing simulations possible
after the Xilinx IMPLEMENTATION
Creating a new bit file
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 128

Today’s Individual Xilinx Lab Work
10. Perform a Xilinx IMPLEMENTATION
•
Xilinx IMPLEMENTATION maps the schematics to the
FPGA resources (CLBs and wires)

•
If the mapping is complete then there are no errors but
there can be warnings
• Mapping allows real components to be considered, hence
timing simulations
Xilinx IMPLEMENTATION consists of 3 major steps
•
•

Synthesis to translate the schematic to a netlist file after
converting the schematic to a VHDL file
Implement Design which consists of
• Translate, Map, Place & Route
Generate Programming File to generate the bit file
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 129

Today’s Individual Xilinx Lab Work
10. Perform a Xilinx IMPLEMENTATION


Click on Design Summary (out of date) to be able to see number
of errors and warnings
Right click on Generate Programming File and select Rerun All


We will do the Synthesis, Implement Design and Generate Programming File
steps altogether
•
Even though we already did the synthesis, we will do it again to get
practice on this as we will do it many times
•
The question mark next to ppm1.sch is changed to a check mark
Wait until the IMPLEMENTATION completes
•
If it does not complete, it stops at one of the steps
 We have to read the errors to read on the Design Summary panel


Once completed, there are no marks next to any one of the steps
just performed
See the Project Navigator window on the next slide
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 130
Today’s Individual Xilinx Lab Work

10.
Perform a Xilinx IMPLEMENTATION

The Project Navigatorwindow looks like this after the
IMPLEMENTATION is completed successfully :
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 131

Today’s Individual Xilinx Lab Work
10. Perform a Xilinx IMPLEMENTATION

For the current IMPLEMENTATION we will get




•
Read the warnings by clicking on 68 Warnings on the
Design Summary window whether or not the Xilinx
IMPLEMENTATION completes
We often check Design Summary for the warnings and the
FPGA utilization



0 Errors
68 Warnings 2 higher than the Experiment 1 project due to
the unused OFL, and CO outputs of the new 4-bit ADDer
6% Slice utilization
Most warnings we check are in the Synthesis section
The FPGA utilization is lower than expected if there are
errors or warnings that must be corrected
In Experiment 2, the number of warnings will be 68

This number will change depending on the experiment
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 132

Today’s Individual Xilinx Lab Work
11.
Perform timing simulations on the 4-bit ADDer



Timing simulations are based on delays for the components and
signal propogations on the wires
Xilinx ISE records these delay only if we perform a Generate
Post-Place & Route Simulation Model
We select this option by expanding the Place & Route step
Click here
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 133

Today’s Individual Xilinx Lab Work
11.
Perform timing simulations on the 4-bit ADDer



Timing simulations are based on delays for the components and
signal propogations on the wires
Xilinx ISE records these delay only if we perform a Generate
Post-Place & Route Simulation Model
Since the Generate Post-Place & Route Simulation Model step has
a question mark next to it, we have to perform the step by double
clicking on it
Double click on this line
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 134

Today’s Individual Xilinx Lab Work
11.
Perform timing simulations on the 4-bit ADDer

The Generate Post-Place & Route Simulation Model step has a
check mark which means we can do timing simulations
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 135

Today’s Individual Xilinx Lab Work
11.
Perform timing simulations on the 4-bit ADDer

To start the simulation, click on Simulation
DELETE THIS SECOND FA
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 136

Today’s Individual Xilinx Lab Work
11.
Perform timing simulations on the 4-bit ADDer

You will see that the Processes panel has a new selection :
Simulate Behavioral Model (functional simulation)
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 137

Today’s Individual Xilinx Lab Work
11.
Perform timing simulations on the 4-bit ADDer

However, we want timing simulations and so we will click here and
select Post Route
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 138

Today’s Individual Xilinx Lab Work
11.
Perform timing simulations on the 4-bit ADDer
•
We are now ready to perform timing simulations
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 139

Today’s Individual Xilinx Lab Work
11.
Perform timing simulations on the 4-bit ADDer
•
Click on the ppm vhdl name to view the Simulate Post-Place &
Route step
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 140

Today’s Individual Xilinx Lab Work
11.
Perform timing simulations on the 4-bit ADDer
•
Double click here, on the Simulate Post-Place & Route Model step
to start the timing simulation
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 141

Today’s Individual Xilinx Lab Work
11.
Perform timing simulations on the 4-bit ADDer
 To simulate the 4-bit ADDer we need to select its inputs and
outputs
 The adder has 8 inputs : DISP15, DISP14, DISP13, DISP12, RD3,
RD2, RD1, RD0
 The adder has five outputs : Pd3prd, NPDISP15, NPDISP14,
NPDISP13, NPDISP12
 The simulator wire list and object list are not alphabetically
ordered !
 We have to delete all the wires on the wire list
 We click on Objects on the left side to view the object list
 We right click in the Objects panel and select Search to select
the wires one by one
 After we enter a wire name, for example DISP12 and press Enter
the simulator will list a number of wires with this name
 We select and drag the first one to the wire list area
 See the next slide
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 142

Today’s Individual Xilinx Lab Work
11.
Perform timing simulations on the 4-bit ADDer
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 143

Today’s Individual Xilinx Lab Work
11.
Perform timing simulations on the 4-bit ADDer
•
•
To simulate the 4-bit ADDer we need to select its inputs and
outputs
The adder has 8 inputs and 5 outputs
Make sure you select the signals as follows :
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 144

Today’s Individual Xilinx Lab Work
11.
Perform timing simulations on the 4-bit ADDer

Click on Restart on the upper tool bar so that the starting time is 0
seconds

Change observation duration time from 1 microseconds to 5 nanoseconds
by entering 5ns

Apply 0 to all the inputs and note that outputs NPDISP14 takes the
longest time to compute which is 3.455 ns




Note that this is NOT fixed !
From one person to another it will change !
The reason is that Xilinx uses a random placement techniques and so the
components are not placed on the same CLBs from one person to another !
See the next slide
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 145

Today’s Individual Xilinx Lab Work
11.
Perform timing simulations on the 4-bit ADDer

The addition time of (0000) + (0000) takes 3.455 ns
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 146

Today’s Individual Xilinx Lab Work
11.
Perform timing simulations on the 4-bit ADDer
Glitches
tADD
0+0
tADD
0+8
tADD
4+8
tADD
9+4
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 147

Today’s Individual Xilinx Lab Work
11. Perform timing simulations on the 4-bit
ADDer

Do you think there is a possibility of a glitch by
the circuit you designed ?




If yes, which output(s) would have the glitch ?
Which input combination pairs would generate the
glitch ?
Observe the glitch and show it to the TA
Before completing this step, make sure the
circuit in schematic 6 is beautified, the
schematic is saved and a Xilinx
IMPLEMENTATION is done again
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 148

Today’s Individual Xilinx Lab Work
12. Download the Ppm project to the FPGA chip
and play the game and to verify that the
schematic works correctly

Program the FPGA chip

Test the Ppm to see if it is working
•


Play the game on the FPGA board
If it does not work, inspect your circuit in Block 3 and
correct the circuit
If you are sure your circuit is correct then
•
•
Compare your design with the Term Project Check List handout
to see if your design follows the handout
If yes, copy your Experiment 2 folder from the S drive and to
your laptop
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 149

Today’s Individual Xilinx Lab Work
13.
Help your partners complete today’s project
14.
Submit your exp2 project once everyone
completes the design



If all the team members have finished the 4-bit ADDer
design (Step 12 on the previous slide), they will decide
whose project will be submitted
Students will fill out a Term Project Check List handout
so that feedback can be given to them by the grading
TAs
Students will signal to a TA who will copy their project
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 150

Today’s Individual Xilinx Lab Work
15.
Continue Reading the Term Project handout
Study and play the other two types of the Ppm game to
think more about the our machine player’s strategy



Human vs. human : ppmhvsh
Machine vs. machine : ppmmvsm
•

Think about the playing strategy of the machine player that will be
designed
Also read slides at the end to learn about the software,
Project Manager, Schematic design and other related topics
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 151

Understand Critical Wires
RD : 4 bits
 The random digit
R1D : 4 bits
Next random digit
R2D : 4 bits
The random digit after next random digit
DISP : 16 bits
 They represent the four position displays
 In Hex
 DISP15-DISP12 : The leftmost position display, PD3
 DISP11-DISP8 : position display PD2, etc
NPDISP : 16 bits
 The result of RD to each display digit
 In Hex
 NPDISP15-NPDISP12 : The leftmost position, PD3, value + RD
 NPDISP11-NPDISP8 : Position display PD2 value + RD
NPSELDISP : 4 bits
 Selects one of NPDISP display values
 In Hex
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 152

Understand Critical Wires
BRWD : 4 bits
 Basic reward
 In Hex
 The digit played and also minimum points earned
 It is selected from RD or NPSELDISP
 Based on how the player played : Directly or with an addition
Brwdeqz : 1 bit
 BRWD is zero when it is 1
PDPRD : 4 bits
 Display overflow bits after addition
Pdprd : 1 bit
The display overflow bit of the position played
Selplyr : 1 bit
 The current player
 If it is 0, it is the human player, otherwise, it is the machine
player
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 153

Understand Critical Wires
P1SEL : 4 bits
 The position played by the human player
P2SEL : 4 bits
 The position played by the machine player
PSEL : 4 bits
 Position Select bits of current player
ENCPSEL : 2 bits
 The number of the position played
EQ : 4 bits
 The equality of the four displays to the digit played
NSD : 2 bits
 The number of similar digits, i.e. the adjacency information of the
position played
RWD : 8 bits
 The regular reward points calculated based on adjacencies
 In Unsigned Binary
CODERWD : 8 bits
 The code reward points calculated based on the code digits
 In Unsigned Binary
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 154

Understand Critical Wires
P1PT : 8 bits
 Player 1 points
 In Hex
P2PT : 8 bits
 Player 2 points
 In Hex
PT : 8 bits
 The points of the current player
 In Hex
NPT : 8 bits
 New player points for the current player
 In Hex
Ptovf : 1 bit
The points overflow
 if it is 1, the new player points is above (255)10
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 155

Understand Critical Wires
P1add : 1 bit
 Player 1 adds when it is 1
P2add : 1 bit
 Player 2 adds when it is 1
Add : 1 bit
 The current player adds when it is 1
P1skip : 1 bit
 Player 1 skips when it is 1
P2skip : 1 bit
 Player 2 skips when it is 1
P1played : 1 bit
 Player 1 has played when it is 1
P2played : 1 bit
 Player 2 has played when it is 1
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 156

Understand Critical Wires
DISPSEL : 2 bit
 Selects one of four values for displays




00 Selects position displays (displays that RD is played on)
01 Selects player points
10 Selects next two random digits
11 Selects discovered code digits
Add : 1 bit
Shows that the current player has selected to add
Stp1pt : 1 bit
 Store Player 1 points
Stp2pt : 1 bit
 Store Player 2 points
Grd : 1 bit
 Signals to generate a new random digit
 The random digit counter output is stored as P2RD while P2RD and
P1RD are shifted to generate the new P1RD and RD
Bpds : 1 bit
Blink one or all displays slowly
Bpdf : 1 bit
Blocks a display fast after a display overflow
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 157

Understand Critical Wires
Clear : 1 bit
 Clear FFs, registers, counters, etc. during reset in Block 2, Block 4
and Block 6 so that it can play again
Clearp2ffs : 1 bit
 Clears Player 2 FFs, counters and registers
Clff : 1 bit
 Clears FFs in Block 2 so that the next player can play if there is no
overflow
S1 : 1 bit
 State 1 where when it is 1, the Ppm is in state 1
P2sturn : 1 bit
 Signals that Player 2 has the turn
 It is 1 when the Ppm is in state 4
Sysclk : 1 bit
 System clock of the operation diagram at 6 Hz
 P2clk : 1 bit
 The clock signal of Player 2 at 48 Hz
 Rdclk : 1 bit

The random digit counter clock at 192 Hz
CS 2204 Spring 2014 Experiment 1-2 Lab 5 Page 158