Transcript FCRP Logo - International Technology Roadmap for

ERD Logic Section for 2009
ITRS Logic Workshop
San Francisco, Ca. Dec 14, 2008
George Bourianoff facilitating
Agenda

Determine content for 2009 ERD logic section
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–
–
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Add Potential Solutions table for Carbon Based Electronics
Discuss linkage to materials and architecture sections
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Section structure
– Transition table
– Table 1 – “CMOS Extension”
– Table 2 – “Beyond CMOS”
– Potential solutions table
Determine Technology Entries (TEs) for 2009
Determine transition table entries for 2009
Solicit writing volunteers for 2009
How can we improve the integration? (better links to key materials
properties table, …)
Approximate timeline for 2009
Proposed Chapter Structure
• Transition table - same structure 2007
• Table 1 - “CMOS Extension”
– Include (devices with FET functionality)
• Low dimensional structures
• III-V and Ge channel replacement structures
• Carbon-based material channel replacement
structures
• BTBT devices ?
• ??????
Proposed Chapter structure (Cont)
• Table 2 “Beyond CMOS” devices
– Category A “Digital Functionality”
•
•
•
•
Spin Devices
NEMS switches
Atomic and molecular switches
?????
– Category B “Non Digital Functionality”
•
•
•
•
Spin devices
Multi-ferroic devices
Molecular devices
???
Proposed Chapter structure (Cont)
• Proposed solution table for carbon based
Nanoelectronics
Discussion of Section Structure
• Transition table
– discussion
• CMOS extension Table
– discussion
• Beyond CMOS Table
– Discussion
• Potential solution table
• Architectural linkage paragraph
High performance logic table 2007
Device
FET [A]
Typical example devices
Si CMOS
FET Extension
1D structures
Channel
replacement
CNT FET
III-V compound
semiconductor and
NW FET
Ge channel
NW heteroreplacement
structures
SET
Molecular
SET
Crossbar latch
Molecular
transistor
Molecular QCA
Ferromagnetic
logic
Moving domain
wall
M: QCA
Spin Gain
transistor
Spin FET
Nanoribbon
transistors with
graphene
Cell Size
(spatial
pitch) [B]
Density
2
(device/cm )
Spin transistor
Spin Torque
Transistor
Projected
100 nm
100 nm [D]
300 nm [I]
40 nm [O]
10 nm [U]
140 nm [Y]
100 nm [C]
Demonstrated
590 nm
~1.5 m [E]
1700 nm [J]
~200 nm [K, L]
~2 m [V]
250 nm [Z, AA]
100 m [AB]
Projected
Demonstrated
Projected
Demonstrated
Projected
Demonstrated
1E10
2.8E8
12 THz
1.5 THz
61 GHz
5.6 GHz
4.5E9
4E7
6.3 THz [F]
200 MHz [G]
61 GHz [C]
220 Hz [H]
6.1E9
3.5E7
>1 THz
>300 GHz
61 GHz [C]
Data not available
1E12
2E7
1 THz [W]
100 Hz [V]
1 GHz [U]
100 Hz [V]
5E9
1.6E9
1 GHz [Y]
30 Hz [Z, AA]
10 MHz [Y]
30 Hz [Z]
4.5E9
1E4
40 GHz [AC]
Not known
Not known
Not known
Projected
3E-18
3E-18
3.00E-18
5E-17 [X]
~1E-17 [Z]
3E-18
Demonstrated
1E-16
1E-11 [H]
1E-16 [J]
6E10
~2E9
10 THz [Q]
2 THz [R]
1 GHz [O]
1 MHz [P]
1×10–18 [O]
[>1.5×10–17 ] [S]
–17
8×10
[T]
3E-7 [V]
6E-18 [AA]
Not known
Projected
238
238
61
10
1000
5E-2
Not known
Demonstrated
1.6
1E-8
Data not available
2E-4
2E-9
5E-8
Not known
Operational Temperature
RT
RT
RT [M, N]
RT
RT
RT
Materials System
Si
RT
CNT,
Si, Ge, III-V,
In2O3, ZnO, TiO2,
SiC,
379
InGaAs, InAs,
InSb
III-V, Si, Ge,
Organic
molecules
Ferromagnetic
alloys
Si, III-V,
complex metals
oxides
62
91
244
32
122
Switch Speed
Circuit Speed
Switching
Energy, J
Binary
Throughput,
2
GBit/ns/cm
Research Activity [AD]
[>1.3×10
–14
] [S]
Table 1 Proposed changes – “High
Performance” >”CMOS Extension”
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•
•
•
•
•
Low dimensional structures :Carbon Nanotube FETs,
nanowire FETs, Nanowire heterostructures, GNR
FETS.
High mobility channel replacement FETs including III-V
and Ge
Single electron devices - Move to table 2
Molecular devices including atomic switches- focus on
molecule on CMOS architecture (CMOL) concept Move to table 2
Ferromagnetic and coherent spin devices – Move to
table 2
Add Band to Band Tunneling Devices ??
Proposed CMOS Extension Entries
• Low dimensional structures (nanowires)
• III-V and Ge channel replacement
structures
• Carbon-based material channel
replacement structures (CNT and GNR)
• BTBT devices ?
• ??????
2007 Alternative Device Table
Resonant
Tunneling
Diodes
Multi-ferroic Tunnel
Junctions
Single Electron
Transistors
Molecular Devices
Ferro-Magnetic
Devices
Frequency
Coherent Spin
Devices
State
Variable
Charge
Dielectric and
magnetic domain
polarization
Charge
Molecular
conformation
Ferromagnetic
polarization
Precession
frequency
Response
Function
Negative
differential
resistance
Four resistive states
Staircase I/V from
Coulomb
blockade
Hysteretic
Nonlinear
Nonlinear
Class—
Example
Mobile
Multi-ferroic tunnel
junction
Voltage tunable
transfer function
CMOL, cross bar
latch
Amplifiers, buses,
switches
Spin torque
oscillator
Architecture
Heterogeneous
Morphic
Heterogeneous,
morphic
MQCA, morphic
Morphic
Application
Elements in hybrid
magneto electric
circuits
Analog pattern
matching
Associative
processing , NP
complete,
Elements in hybrid
magneto-electric
circuits
Microwave
power, tunable
rectifiers
Comments
Additional
functionality
Density,
functionality
Density, cost
functionality
Radiation hard,
environmental
rugged
RF functionality
Status
Demo
Demo
Demo
Demo
Simulation
Material
Issues
Stray charge
RT DMS
Table 2 proposed changes “Alternative
Information Processing” > “Beyond CMOS”
• Resonant Tunneling Diodes – Move to transition table
• Digital Functionality
– Multi-ferroic devices
– Spin devices
– Single Electron devices
• Non digital functionality
–
–
–
–
–
Molecular Devices – CMOL
Bi-layer graphene devices
MQCA
Frequency Coherent Spin Devices
RF devices
• Do we want to include some “architecture driven”
device?
Proposed “Beyond CMOS” entries
• Category A “Digital Functionality”
–
–
–
–
Spin Devices
NEMS switches
Atomic and molecular switches
?????
• Category B “Non Digital Functionality”
–
–
–
–
Spin devices
Multi-ferroic devices
Molecular devices
???
2007 Transition table
IN/OUT
Rapid Single Flux Quanta (RSFQ)
CMOS extension-III-V channel
replacements
Impact Ionization MOS
Nano Electro Mechanical Systems
(NEMS)
OUT
Reason for IN/OUT
RSFQ devices, systems and
circuits have been developed,
prototyped, and fabricated.
They could become an
important technology if the
correct market driver emerges
Comment
Design and fabrication lines
for RSFQ systems exist.
Cryogenic operation, cost and
material integration issues
limit application space
IN
Low bandgap, compound III-V
semiconductors can
potentially improve transistor
performance
Research on compound III-V
semiconductors on SI
substrates has increased
significantly over the last 2
years
Possible Future
Simulation results showing
very low sub threshold slopes
indicate potential for low
power operation
Reliability remains an issue
may be included in future
editions
Possible Future
Potential for ultra low leakage
device based on nano relay
operation
Issues associated with
stiction, speed, active power
and reliability are being
studied –may be included in
future editions
Lateral interband tunneling
transistor
Possible Future
Floating gate MOS devices
Possible Future
Potential to utilize gate
modulated interband
tunneling to reduce
subthreshold slope
Devices with nanocrystals
embedded in gate allow
circuits with tuneable
thresholds. Potential for low
power circuits
May be included in future
editions
May be included in future
editions
2009 Transition table proposed
Technology
Status
Reason
RTD
out
No viable logic
functionality
Bi-layer tunneling
devices
In
Significant
theoretical work in
NRI
Band to band
tunneling devices
In
NEMS
In
RSFQ
Possible future
device
Comment
Has been tracked
for multiple revisions
New topics for discussion
– Should we broaden the “CMOS extension”
table to include Low Power” and “Low
Standby Power” entries?
– Pros
• Would align better with ITRS System Drivers
• Would reflect motivation of much research
– Con
• Would significantly complicate chapter
organization
• Would be orthogonal to the historical “tracking”
function of the Table
Technology Entries(1)
• FET extensions
– Low dimension Channel replacement
category
• CNTFETS and Nanowire FETS
• Discuss CNTFETs with PIDs
– High mobility channel replacements
• Send III-V and Ge to PIDs
• Graphene Nanoribbon devices
SETs
• Move to Table 2
– Some recent work still suggests logic
applications
– Emphasize non logic applications
(recognition)
– SETs have been around for a long time
– Stray charge will always be problem
Nature of Nanotechnology advance online
Molecular devices
• Move to table 2
• Emphasize potential applications in
crossbar architectures, CMOL
• Recent progress will be reviewed
• Some people believe strongly that the
technology has great potential
Ferromagnetic and spin transistor
• Merge categories and move to table 2
• Emphasize non volatile functionality
• Include MQCA and domain wall
applications
• STTRAM research is driving progress in
materials and process
Band to band tunneling devices
•
•
•
•
Include as a category in table 1 ???
Include other steep SS devices
Most devices suffer from low Isat or high Vd
CNT tunnel FETs
Resonant Tunnel Diodes
• Recommend moving to transition table
• Pros
– Not much recent progress for any logic
application
• Cons
– It is an interesting device with NDR
– Many people feel strongly about it
Multiferroic and magnetoelectric
devices
• Include multiferroic tunnel junctions,
magnetoelectric amplifiers,
magnetoelectric drivers and detectors
• Significant progress in RT mutiferroic and
magnetoelectric materials e.g. BFO
Single Electron devices
• Remove from table 1 -keep in table 2
– Active research for Boolean applications
quantum dots
– Potential Non Boolean logic applications such
as image recognition still receiving attention
– Stray charge still an issue
Potential solution table for carbon
based nanoelectronics
• Build on ITRS “potential solution” format
• Separate into material driven requirements
and novel device driven requirements
• Tie closely and directly to ERM
ERM table of applications
Table ERM2
MATERIALS
ERD MEMORY
Applications of Emerging Research Materials
ERD LOGIC
LITHOGRAPHY
FEP
INTERCONNECTS
Nanotube
Low Dimensional
Materials
Macromolecules
Nano-mechanical
Memory
Molecular memory
Nanowire
Graphene and
graphitic structures
Molecular devices
Self Assembled
Materials
Nanotubes
High-index
immersion liquids
Resists
Imprint polymers
Metal nanowires
Novel cleans
Selective etches
Low-κ ILD
Selective depositions
Sub- lithographic
patterns
Selective etch
Enhanced
dimensional control
Deterministic doping
Selective deposition
ASSEMBLY AND
PACKAGE
Electrical
applications
Thermal applications
Mechanical
applications
Polymer electrical
and thermal/
mechanical property
control
Selective etch
High performance
Selective deposition capacitors
Semiconductor spin
transport
Spin Materials
MRAM by spin
injection
Ferromagnetic (FM)
semiconductors
FM metals
Tunnel dielectrics
Passivation
dielectrics
Complex Metal
Oxides
Interfaces and
Heterointerfaces
1T Fe FET
Fuse-anti-fuse
Electrical and spin
contacts and
interfaces
Multiferroics (Spin
materials)
High performance
capacitors
Novel phase change
Electrical and spin
contacts and
interfaces
Contacts and
interfaces
Proposed structure - table 1
First Year available for Production
2009
2010
4 5 nm
2011
2012
2013
3 2 nm
2014
2015
2016
2 2 nm
2017
2018
2019
16 nm
2020 2021
2022
11nm
Materials & Processes for Carbonbased Nanoelectronics
CNTs
density (pitch)
growth control (type)
doping
contacting
alignment
variability
Graphene
Manufacturable deposition
patterning
edge effects
contacting
dielectrics
bilayers
variability
This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution.
Research Required
Development Underway
Qualification / Pre-Production
Continuous Improvement
2023 2024
Proposed structure –table 2
Carbon-based Nanoelectronics
Devics
Digital CNTFET
Analog CNTFET
digital GNRFET
Analog GNRFET
bilayer devices
Quantum interference devices
This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution.
Research Required
Development Underway
Qualification / Pre-Production
Continuous Improvement
Coupling to ERM
ERM
Key Challenges
Carbon Nanotubes -Control of bandgap and metallic
versus semiconducting
Nanowires
2007 Status
Dai: >90% Semiconducting
-Control of carrier type and
concentration
Control with ion adsorption
-Electrical properties must not
degrade when embedded in a
dielectric
-Control of location
“small” degradation reported
-Control of orientation
Control with E-Field, Quartz steps
self assembly (Poor)
Control of contact resistance
High Variability
-Control of location and
orientation
Catalyst location & 111 growth for
large diameter NW
Progress
CNT pitch needs to be ~30nm to
achieve high current
Dai: Control location with catalyst
Contact resistance must be
reduced below 1 KΩ
-Performance exceeding
patterned materials
III-V Alternate
Channel Materials
-Catalyst and processing
temperatures compatible with
CMOS
Ti is compatible
CMOS Compatibility
Surface passivation
Gate electrode & dielectric
compatibility and control
Contact resistance
Not in 2007
No viable for contacting.. No
Gate electrode & dielectric
compatibility and control
Contact resistance
CMOS Compatibility
Surface passivation
Gate electrode & dielectric
compatibility and control
Contact resistance
Compatibility with CMOS
Processing
No viable for contacting.. No clear
advantage over scaled Si
Not in 2007
High resistivity of N type Ge – huge
problem for CMOS
Poor: SiC decomposition,
exfoliation
Patterning for bandgap control
(<2nm width
-Edge passivation
-Deposition of dielectrics
-Low contact barrier for transport
-Repeatability of switching
mechanisms
-FM semiconductors with
Tc>350K & carrier mediated
exchange
-Semiconductors with long spin
coherence times
-Materials and interfaces to allow
efficient spin injection from FM
materials to semiconductors
-CMOS Compatibility
-Control of defects and interfaces
HfO2 demonstrated
-Low spin decoherence interfaces
Bulk: 195K, GeMn Nanostructure
reports >350K; carrier mediated
exchange not verified
Complex Metal
Oxides (FE FET)
Applications
(FERAM, Spin
memory, Spin
Logic, Fuse-antiFuse)
Complex Metal
Oxides (Fuse-antifuse)
Strongly
Correlated
Electron Materials
(Novel Logic)
III-V and Ge
Alternate Channel
Materials
New for 2009
-Control of defects and interfaces
during fabrication
-Degradation of materials
properties during use
-Reliability of the fuse mechanism
-Identification of dynamic
properties compatible with logic
applications
Control of stoichiometry, vacancy
concentration, and stress
-Material compatibility with CMOS
processing
-Surface Passivation
-High K compatibility and
interface property control
-Demonstration of high mobility
n& p channel devices
-Strategy for integration of n & p
channel devices
Coupled electronic and
-Co
ferromagnetic states reported at
heterointerfaces
Writing volunteers
• People or groups to research and write
text for one or more of the technology
entries
– Need informed but unbiased contributors
Should we include Future Integrated
Nanoelectronics chart?
Other than charges
Charge-based
CMOS-based
Top-down
Bottom-up
Sub-60mV/dec
Bulk
S-S/D
Spin
Ballistic
Strain Si （110）
GOI
FD-SOI
3D CNT GNR
Nanowire Nanowire
High-k/metal-G
Variations Ge
Atom molecular
III-V
DFM High yield
Optical Int.
2005
Main stream Si
Year
2020?
2035?
Fusion, No boundary
1. More Moore
(CMOS Extension)
3. Beyond CMOS
ERD Working group Japan
2. More Than Moore
Algorithm
33
Evolution of Extended CMOS
Elements
Existing technologies
Opt. Int.
III-V
Sub-60
Atom CNT
Spin
Atom
New technologies
Spin
Beyond CMOS
ERD-WG in Japan
year
34
2009 ITRS/ERD Major Deliverables and Timeline
ERD Chapter due August 21, 2009
Major Tasks and Time Line
 Outlines for Memory, Logic, Architecture, Mat’l March 18
 Technology Requirements Tables
April 6
 Guiding Principles Section
June 1
 Draft Text Completed
 Memory, Logic, Architecture, MaterialJuly 6
 Functional Organization & Critical Review
July 20
 Scope, Difficult Challenges, etc.
July 27
 Chapter Completed
August 21
 Chapter Frozen
Sept. 15
Major Face-to-Face Meetings in 2009
 ITRS/ERD Meeting near Brussels, Belgium
March 18
 ITRS/ERD Meeting at Semicon West (SF, CA) July 12
 ITRS/ERD Meeting near Hsinchu, Taiwan
Nov. 30
35 ERD WG 12/06/08 & 12/14/08
Work in Progress --- Not for Publication