Transcript CMOS VLSI Design

CMOS VLSI Design
Technology, Business Model and
Future Trends
Plenty of Room at the bottom??
• Currently at 45 nm process node and soon to
be on 28 nm
• Lithography was seen to be a major obstacle
(dealt with using Immersion or X/EUV)
• Moore’s Law still holding but for how long?
• Transistors on die doubling and so is the Fab
cost (Standing at close to 5bn for latest tech)
Materials Innovations
• STI (Shallow Trench Isolation), CMP (Chemical
Mechanical Polishing) and other process
enhancements are now part of all
manufacturing
• Cu Interconnects replacing Al
• Low-K dielectric for successive metalization
• High-K Oxide for the Gate
• Metal Gate replacing Polysilicon
What about Transistor?
• Traditional CMOS structure being questioned
• Tri-gate and other FINFET structures likely to
be adopted going forward
• Primary reason being Power (esp. Leakage
Power)
• Power density of a nuclear reactor in a server
class microprocessor
• Power coming ahead of feature size or cost
Alternatives to Silicon??
• GaAs, SiC, InP and so on
• How about nanotechnology? Carbon
Nanotubes?
• Silicon Ecosystem is hard to beat and drivers
for such transition are not there.
• Industry reluctant to move to 450 mm wafers
(due to cost reasons) even though good
enough rational exists for it.
Design Process
• Front End (Architecture, RTL Coding, Test
Bench, Lint, CDC checks, Synthesis, DFT, STA,
Power Estimation)
• Back End (Floorplan, PowerPlan, Timing
Constraints refinement, Placement,
Optimization, Global Routing, CTS, Detailed
Routing, Timing Closure and Physical
Verification
• ECO (Engineering Change Order)
Skills Development
• FPGA are great platform to learn and practice
design skills but be fully aware that ASIC requires
some extra work that is not exposed to designers
in FPGA world
• Majority of the design bugs are still functional
bugs; despite increasing complexity of the CMOS
technology
• Any software engineer can write verilog (its
almost like C anyways) until they hear about
“CLOCK”
Skills Development (Cont.)
• PERL (If you have not heard of it, please
google it right away if you ever plan to design
chips)
• Same for TCL
• Some aspects of software development
process are relevant to chips as well (Version
Control, Build Process, Bug Tracking etc.)
• Finally, knowledge of end-user application will
make you better architects
Design Tools
• Hammer, Wrench and Pliers
• EDA world inhabited by superb software
engineers who like to create smart algorithms
and innovative UI but they rarely design chips
• No set of tools will let you build chips just using
the tools alone; i.e. it is inevitable that you will
need to build some custom scripts, tools to patch
together a flow
• With evolution of technology, some of the
concerns like signal integrity or power grid design
etc now require as much attention as gates
Intellectual Property
• Holy Grail of modern chip design is the
assembling them like Lego bricks using preexisting sub modules
• In no chip has it worked that way, unless a
particular IP has been used and built into
working silicon already
• Intellectual Property does not equal RTL code!
• Despite all these problems, no SoC is ever
built from scratch.
Section II
BUSINESS MODEL
End Markets
• 3 Cs (Computers, Communications, and
Consumer)
• Industrial and Automations is also a significant
users
• Migration to CMOS for digital design as well as
for other technologies like RF or Image Sensor
• Mixed signal chips in wireless world
• More and more applications are implemented
using digital (Audio, Video, Motor Control, etc)
Integrated Device Manufacturer
• Chips, screws, boxes and software (IBM, DEC)
• Today even design, manufacture and
marketing of chips is rarely done by same
company (Intel)
• Fabless Model is well developed and has
proven successful
• EDA model is somewhat successful and IP
business model is questionable
ASIC vs FPGA
• Number of design starts every year are shrinking,
esp in recession
• FPGAs are attractive alternative for any markets
not requiring strict power, cost and size budgets
• High volume markets still require custom ASICs
• FPGAs are now able to meet fairly high
performance requirements; networking gear is an
ideal market for them
Best of both worlds??
• How about programmable array on a custom
ASIC
• May be appropriate for some niche markets
• The design starts are decreasing but the
design teams needed to execute very large
chips (afforded by more available transistors)
on latest technology node requires large
design teams
GHz, now it really hurts!
• Until the beginning of this decade there was
an implicit GHz race among high-performance
chip makers but soon the lesson was learned
that even if technically feasible it is not the
right way to performance
• Multi-core is the new new thing, if you have
not read any research from 20 yrs ago
• In any case, mobile phone processors are not
at 1 GHz and possibly 2 or 4 cores on the die
Memory, IO and Usability
• DDR, Flash
• USB, PCI Express
• Hot plugged, power managed and autoconfigured IO
• All IO technologies now serial (LVDS) instead
of wide parallel CMOS
• Still there are too many to choose from
Semiconductor Market
• 300bn per year
• Majority of it is digital IC
• IDMs still sell lot of standard parts like microcontrollers, memories etc but fabless is not
becoming larger and larger part of the market
• Eventually, standard parts will be needed for
specialty markets like industrial, automotive,
power, sensors, control etc but rest will be
digital CMOS and very likely fabless
Newer Markets or More Integration?
• Health Care, Biomedical, Renewable Energy
(Solar Cells etc.)
• LCD, LED, OLED displays
• Laser projectors
• 3 Cs will remain significant users of standard
CMOS digital semiconductor but may become
commoditized
• Innovations will be sector(application) specific
EDA and IP
• ARM is the only surviving IP company of
significant size
• Despite superficial similarities, Software
business model does not transplant to chip
design
• EDA model is moderately successful, 3 bn EDA
serving 300bn semiconductor industry
• IP and Design Services model is not scalable
Section III
FUTURE TRENDS
Reading Tea Leaves
• There may be market for 5 computers world
wide
• Who will need a computer in their home?
• Who can possibly need more that 640K of
RAM?
• Given such illustrious company, I am not shy
to make a fool of myself
Fabless is the future
• It may even be present depending on who you
ask
• Need a way to spread risk
• IDM model declining due to capital
requirements
• Fabless model may also face the same issues;
hard to compete with dot coms for VC dollars
• India has chance to catch up in terms of
design skills once technology nodes stabilize
Costs
• Latest technology node fabs cost close to 5 bn
• It can be trouble if utilization drops below 90%
• 20 yrs ago DRAMs were the drivers of
technology, then microprocessors and now
flash memories
• Digital CMOS IC development costs are also
escalating, easily 20-30 mn for significant size
SoC; implies high volume markets to be able
to amortize the development costs
Convergence is cool
• Your laptop is your only computer
• Tomorrow, your iPhone may be your only
computer
• Your computer is your media player, will it also
be your set top box?
• Your mobile phone is also your home phone
• Voice or Video: everything is just an IP packet
• Telco Switches or CISCO routers?
Internet
• Bubble that indeed changed the world
• Broadband (wireless or wired) will be the only
media-agnostic communication pipe to the
consumer
• Most people on the planet will first experience
internet on their mobile and not computer
• Roughly, every other person on the planet has
a mobile
Skip a grade
• Developing countries like India can skip a few
steps in technology migration
• With china quickly climbing the value added
food chain of technology development, latest
technology will become affordable in
developing world (Wireless, Media Players,
Electric Cars)
• Indian engineers and manufacturers can no
longer live in splendid isolation
To design, to make or to service?
• India has sadly missed the boat on
manufacturing semiconductors (even if 5 bn
fab can erected, it is impossible to keep it fed)
• Design Services: low margin, cyclical business
that does not scale
• Design aka fabless is fairly reliable business
model (although comparatively costly) Costs
can be mitigated by doing all engineering
work in India
Test and Assembly
• There is an opportunity here
• Lacking manufacturing capability is a bit
disadvantage but english-speaking skilled work
force is a plus
• Maturing industry will fragment further and will
look for cheaper destinations
• If India can successfully create a fabless industry,
it would match china’s manufacturing capability
and will be complementary
Questions
• Fabless Semiconductor Association (recently
changed name)
• Latest scoop on tools: deepchip.com (John
Cooley)
• Eetimes.com, electronicnews.com
• CMOS VLSI Design (Neil Weste)
• Intel Technology Journal