Transcript Presentation: Comparison of Strategies for Redundancy to

Twin Logic Gates –
Improved Logic Reliability by Redundancy
concerning Gate Oxide Breakdown
Hagen Sämrow, Claas Cornelius, Frank Sill,
Andreas Tockhorn, Dirk Timmermann
03.09.2009, Natal
Institute of Applied Microelectronics
and Computer Engineering
University of Rostock
Outline
Motivation and Basics
Approaches for reliability enhancements
Gate oxide breakdown
Redundancy strategies
Redundancy on different levels
Results
Discussion
Conclusion / Outlook
2
Motivation – Known approaches
Reliability
Transient failures
Soft error resilience
Permanent failures
Initial failures
Failures occuring
at runtime
Yield enhancements
Little effort put into
-
Hardening techniques
-
Layout modifications
-
Reusing debug resources
-
Redundancy
lifetime reliability
enhancements
for redundant flipflops [Mitra]
3
Basics – Gate oxide breakdown
Gate oxide breakdown – GOB:
Point of time a conducting path between gate and substrate is
generated
Mainly dependent on:
Gate oxide thickness
Electrical field at the gate
Causes:
Sudden extrinsic overvoltage: ESD – Electro-Static Discharge
Slow intrinsic destruction over time: TDDB – Time-Dependent
Dielectric Breakdown
4
Basics – TDDB
Initial traps
Physical mechanism:
trap creation
Finally: Hard breakdown
During operation: generation of overlapping traps
Poly Silicon
R
->00
IR
SiO2
R
Substrate
Soft breakdown:
Creation of a
conducting patch
Increasing current flow
Heat dissipation
Thermal damage
5
Basics – TDDB
Finally: Hard breakdown
Model by Renovell et al.
Follows new research results
Gate oxide breakdown harms an affected transistor and its associated cell
with a modified delay
Whole circuit fails if the timing between the cells is no longer balanced
6
Basics – Scaling issues
Scaling increases the gate oxide breakdown problems:
Increasing number of transistors within a die
Decreasing gate oxide thickness
Increase of the electrical field due to non-ideal supply voltage scaling
E1
scaling
E2
t ox1
l1
l1 > l2
t ox1 > t ox2
t ox2
l2
E1< E 2
7
Redundancy strategies
Basic multiplier
Block duplication
Gate duplication
Transistor duplication
8
Simulation setup
Wallace multiplier
Transistor level simulations with HSpice
Industrial 65 nm gate library
Gate oxide breakdown model of Renovell et al.
Implementation of cells with transistors with standard
threshold voltage (SVT) and high threshold voltage (HVT)
9
Ratio to basic multiplier [%]
Results – No defects
Design parameters
Block duplication SVT
Block duplication HVT
Twin Logic Gates SVT
Twin Logic Gates HVT
Transistor duplication SVT
Transistor duplication HVT
10
Results – Reliability with defects
Simulation results
Duplication
+/-
No
26.72
0%
Block
21.17
- 21 %
28.42
+6%
44.34
+ 66 %
with HVT-Cells
54.71
+ 105 %
Twin Logic Gates
72.52
+ 171 %
with HVT-Cells
80.97
+ 203 %
with HVT-Cells
Transistor
R(t) [%]
MTTFGOB
time units t
11
Results – Discussion
Why is the gate level duplication
(Logic Twin Gates) better than
transistor duplication?
Both implementation only differ in
the duplication of the transistor
stacks
Defect_net 2 is charged to a
voltage related to the GOB



Current flow from drain to source of the
middle transitor is rather pinched off
due to the defect (higher voltage level
between lowest two transistors)
Increased fall time of the defect stack
Transistor duplicated stacks are slightly
slower due to the cross links
12
Results – Graceful degradation I
Increase of the delay with rising defects
Twin Logic Gates SVT
Twin Logic Gates HVT
Transistor duplication SVT
Delay [ns]
Transistor duplication HVT
No duplication
Number of defects
13
Results – Graceful degradation I
Power Logic Twin Gates [mA]
Increase of the delay with rising defects
due to increased static power consumption
HVT
HVT overall
overall power
power
SVT overall power
SVT overall
HVT
static power
power
SVT static power
No
No duplication
duplication
Number of defects
14
Conclusion
Need of design improvements for lifetime reliability
Logic Twin Gates promises the most improvements
concerning gate oxide breakdown
Simple integration of Logic Twin Gates into existing
design flows and CAD tools
Graceful degradation behavior in the presence of defects
15
Outlook
Partial duplication of most vulnerable gates or transistors
Usage of benchmark circuits
Investigation of the impact of soft breakdowns
16