Transcript Evaluation of Silicon strips detectors for Roman Pots at ATLAS

Fast sampling for Picosecond timing
Jean-François Genat
EFI Chicago,
Dec 17-18th 2007
Outline
•
Time picking strategies
•
Timing using MCPs
•
Fast Sampling chip
•
Technologies
•
Conclusions
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
Time picking techniques
Discriminators can be:
-
Single Threshold
Derivative’s Zero-crossing
Multiple Thresholds
CFDs (many flavours)
All make assumptions on the signal waveform
depending upon detector + front end processing
Fast sampling and digitization
Extract most of the pulse information if sampling is
fast enough to resolve the signal rise-time
Digital processing allows any kind of time (and amplitude) extraction
Time accuracy depends on the sampling rate and amplitude ranges
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
10-100 GHz sampling
Fast sampling:
High rate sampling and pulse reconstruction knowing the waveform
allows to get accurately:
- Amplitude
- Time
using for instance least squares algorithms (Cleland & Stern)
On-chip digital oscilloscopes, integrated in multi-channel analog
memory chips: Labrador (Hawaii), SAM (Saclay)
Digital signal processing can also be integrated
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
Outline
•
Time picking strategies
•
Timing using MCPs
•
Fast Sampling chip
•
Technologies
•
Conclusions
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
MCPs timing performance
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
Fast signals
0,1
0
0,05
1
2
3
4
5 ns
-0,1
-0,15
-0,2
-0,25
-0,3
-0,35
-0,4
-0,45
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
7621
7113
6605
6097
5589
5081
4573
4065
3557
3049
2541
2033
1525
1017
-0,05
509
1
0
Fast Sampling with Si detectors
Peaking time = 50ns
Input signal 30ns peaking time
(detector + noise)
S/N = 30
Noise
spectrum
Serial, 1/f
Amplitude and time spreads
sigma(a) =2%, sigma(t)= 1.2 ns
A few nanoseconds measured
(M. Friedl, M. Pernicka, Vienna)
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
Fast sampling simulations
Simulated waveforms: White noise added to randomly delayed pulses
Peaking time = 200ps
256 samples
S/N=50
2ns
1ns
Sigma(time) = 6ps
Residual (no noise) : 3ps
Peaking time = 160ps
128 samples
S/N=60
Sigma(time) = 8.3ps
No sensitivity to amplitude distribution
Infinite dynamic range assumed
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
Outline
•
Time picking strategies
•
Timing using MCPs
•
Fast Sampling chip
•
Technologies
•
Conclusions
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
10-100 GHz sampling
Counter and picosecond
Vernier timer
Triggering
discriminators
500 MHz Clock
Wilkinson
AD
Inputs
Analog storage
Read
Cntrl
Output
Write and Read control
Figure 1
Jean-Francois Genat, EFI, Dec
17-18th
Fast sampler block diagram
2007, Chicago
Time
stamps
Blocks
Capacitor bank (SCA):
- number of channels
- depth
- dynamic range
- droop, crosstalk
Timing generator
- time step
- clock frequency
- use Vernier to increase sampling frequency
Triggering Discriminators
- threshold
- speed
- delay
ADC (Wilkinson)
- number of channels
- number of bits
- clock speed
Control and processing
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
Overall:
-
input to SCA bandwidth
temperature sensitivity
calibration
power
Timing generator
Clock input
th
N taps main DLL
tv
M taps Vernier
DLLs
th = Tclock/N,
Increasing delays
tv = Tclock/M
N and M relatively primes
LSB = th-tv
N x M delayed
outputs
Use as much as possible
clock locked looped delays
Routing of delays to SCA critical
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
Digital Delay Lines: DLL
Delay locked loop:
Interpolate delays within a clock period
Delays control
N delay elements t
Clock
Time arbiter
Clock feeds the digital delay line
Phase arbiter locks delays on clock period
M. Bazes IBM, Proc. IEEE JSSC 1985
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
p 75
Phase lock
Clock
DLL output
Phase arbiter
Delay control
Lag
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
Lag
Lead
OK
Delay elements
Active RC element: R resistance of a switched on transistor
C total capacitance at the connecting node
Typically RC = 1-100 using current IC technologies

N delay elements t

N

N
 is technology dependent:
Within a chip
~
1%
a wafer  ~ 5-10%
a lot
 ~ 10-20%
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
the fastest, the best !
[Mantyniemi et al. IEEE JSSC 28-8 pp 887-894]
Time controlled delay
Vdd
Delay controls
thru gates
voltages
PMOS
Delay control
thru Vdd
PMOS
B=A
NMOS
NMOS
Spread=12 ps
Propagation delay t ~ 10-100 ps
CMOS Technology
90nm: t ~ 20-40 ps
65nm in production today
100ps TDC 0.6mm CMOS (1992)
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
Switched Capacitors Array
write
read
reset
Flavours:
- Sampling Cap switched in the loop of an opamp
- Differential implementation
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
Discriminators
Do not need the ps accuracy (reference is the main clock)
Stops the sampling after a (programmable) delay
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
ADC
Wilkinson preferred in terms of power and Silicon area
since heavily parallel
See Eric Delagnes slide:
Fast Wilkinson:
Clock interpolated using a DLL
100 ps counter 10 times faster
Same 12 bit accuracy
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
ILC 130nm Silicon strips chip
Channel n+1
Sparsifier
S aiVi > th (includes auto-zero)
Can be used for
fast decision
Time tag
Channel n-1
reset
reset
Single ramp
10 bits ADC
Analog samplers
Strip
Ch #
Preamp +
Shapers
Waveforms
Counter
CMOS 130nm
ADC
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
Clock 3-96 MHz
Outline
•
Time picking strategies
•
Timing using MCPs
•
Fast Sampling chip
•
Technologies
•
Conclusions
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
Technologies
SiGe
- Not many benefits compared to Deep Sub-Micron CMOS
- In addition CMOS from BiCMOS not as fast as pure DSM CMOS
2006
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
CMOS
Present designs in CMOS:
CERN
HPTDC
IBM
development
.25 mm
.13 mm
Hawaii
BLAB 1
dev 2
TSMC .25 mm
TSMC .25 mm
6 GHz 10b sampling
10 GHz
Saclay
SAM
AMS .35 mm
2 GHz 12b sampling
90nm CMOS available from
MOSIS, Europractice
Drawbacks
- Reduced voltage supply
- Leaks
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
25ps timing generator
6ps timing generator
Outline
•
Time picking strategies
•
Timing using MCPs
•
Fast Sampling chip
•
Technologies
•
Conclusions
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
Backup
J-F Genat, RP220/420 Paris Workshop, Sept 12th 2007
Multi-threshold performance
Multi-threshold: sampling times instead of amplitudes :
- Number of thresholds
- Thresholds values
- Order of the fit:
4-8
equally spaced
2d order optimum
Extrapolated time
MCP PMT single photon signals
Actual MCPs signals
K. Inami
Univ. Nagoya
Tr = 500ps
BUT
tts= 30ps
MCPs segmented anode signals simulation
20 photoelectrons
tts = 860 fs
H. Frisch,
Univ. Chicago + Argonne
N photo-electrons improves as
Jean-Francois Genat, EFI, Dec 17-18th 2007, Chicago
N