Transcript Document
CURRENT SOURCES, CURRENT SINKS
AND CURRENT MIRRORS
CURRENT SINKS AND SOURCES
Characterization of Current Sinks and Sources:
1. Minimum voltage (VMIN) across sink or source
for which the current is no longer constant.
2. Output resistance which is a measure of the
flatness of the current sink or source.
Increasing the output impedance
ROUT of a Current Source
vout
rout
rds2 r1 gm2rds2 gmbs 2rds2
i out
Normally gm 10gmbs 100gds giving us
rout rgm2rds2
CURRENT MIRRORS AND CURRENT AMPLIFIERS
Sources of Errors
If the devices are matched
io W2 L1 1 VDS 2
i i W1L2 1 VDS 1
If VDS1 = VDS2 then
W2 L1
io
ii
W
L
1 2
Matching Accuracy of Current Mirrors
Layout Technique to Remove Layout Error
vout iout gm vgs gmb vsb rds iout r
vout
rout
rds r gm rds gmb rds 1 gm r rds
iout
WILSON CURRENT MIRROR
rout
rds2 gm1 rds1 gm3 rds3
rds1 gm3 rds3 if gm1 gm2
rds2 gm2
This modification to the Simple Current mirror
does ensure an increased output impedance, but
does not ensure VDS1 = VDS2. Vmin obtained in
this configuration is the sum of the voltage,
VDS1(sat) and VDS3(sat), the minimum drain to
source voltage required to keep M3 and M1 in
saturation. Defining VON = VGS – VTH, and
assuming that all transistors have same W/L
ratio, we have VDS1 = VGS1 = VON + VTH and
VDS3(min) = VON and Vmin = 2VON + VTH.
MODIFIED WILSON CURRENT MIRROR
CASCODE CURRENT MIRROR
REGULATED CASCODE CURRENT MIRROR
If all transistors have the same size, VGS2 = VDS1 =
VGS = VDS4, giving us a very good match in mirroring.
CURRENT MIRROR WITH LOW Vmin and
GOOD MIRRORING PROPERTY
We see that in the Cascode
Current Mirror, the voltage
VGG2 was obtained as 2VGS
and hence we had a Vmin of
2VGS – VTH = 2VON +VTH.
However if we can obtain
VGG2 = 2VON + VTH, Vmin can
be reduced to 2VON.
WIDE RANGE CASCODE CURRENT MIRROR
COMPARISON OF VARIOUS CURRENT
MIRROR ARCHITECTURE
Current Mirror
Accuracy
Output impedance
Vmin
Simple
Poor
rds
VON
Wilson
Poor
2
gm rds
Improved
Excellent
Cascode
Excellent
Regulated Cascode
Cascode
Good
Excellent
3
gm2 rds
2
gm rds
2
gm rds
2
gm rds
2VON + VTH
2VON + VTH
2VON + VTH
2VON + VTH
2VON