Transcript Document

INTERPRETATION OF THE SINGLE EVENT UPSET IN
STATIC RANDOM ACCESS MEMORY CHIPS INDUCED BY
LOW ENERGY NEUTRONS
B. Mukherjee1, D. Makowski2
M. Grecki2 , S. Simrock1
1Deutsches
Elektronen Synchrotron, Hamburg, Germany
2Department of Microelectronics and Computer Science, TUL, Poland
12th International MIXDES Conference, 22-25 June 2005, Krakow, Poland
INTRODUCTION
Microelectronic devices operating in the radiation environment of
high-energy particle accelerators are prone to radiation induced
malfunctions.
In particular, the unprecedented, recoverable, short-term failure of
the electronic instrumentation and control systems triggered by
Single Event Effect (SEE) causes great concern.
The SEE is initiated by short excursion of radiation level, particularly
due to neutrons, usually occurs during an unforeseen beam loss
event at high-energy accelerators.
The interaction of densely ionising (high LET) secondary particles
produced via the neutron induced nuclear reaction within the
microchip sets off the SEE.
In this presentation the SEE induction mechanisms of isotopic
(241Am-Be) as well as accelerator produced neutrons in various types
SRAM chips are highlighted.
MECHANISM OF TRIGGERING A SEU
In a microelectronic circuit (M), embedded in the semiconductor
substrate (S) a Single Event Upset (SEU) set off when the interacting
ionising particle deposits sufficient energy in the sensitive volume
enclosing the critical node (N). The SEU triggering mechanism
could be divided in two broad categories:
(a) Direct Interaction
The high energy heavy (HZE)
particle, i.e. of cosmic origin (P)
directly interact with the critical
node (N) by producing a track of
electron/hole pairs, thereby
causing the SEU.
(b) Indirect Interaction
The primary particle, i.e. accelerator produced neutron
undergo nuclear reaction with the primary atom (A)
producing primary knockout atom (PKA) and secondary
charged particle (CP), producing the SEU.
PHYSICAL PHENOMENA GOVERNING THE SEU
The impinging particle deposits the energy (Ed) along the track length
(s) within the semiconductor substrate of density (r):
Ed = L.r.s
(1)
where, L = LET of the impinging particle in the semiconductor material
The electric charged (Qd) required to create an electron/hole pair in the
semiconductor material:
Qd = Ed.q / wehp
(2)
where, q = elementary charge, 1.602 x 10-19 Coulomb and wehp = energy (eV)
required for the production of one electron/hole pair
The minimum (threshold) LET (Lth) required to create an SEU:
Lth = (Qcrit.wehp) / (q.r.smax)
(3)
where, Qcrit = minimum electric charge required to create an electron/hole
pair, smax = maximum track length of the impinging particles of a given LET
in the semiconductor material
PHYSICAL PHENOMENA GOVERNING THE SEU (contd.)
The minimum track length (smin) of the impinging particle required to create
an SEU:
smin = (Qcrit.wehp) / (q.r.L)
(4)
where, L = LET of the impinging particle in the semiconductor material
In case of neutrons, the critical charge (Qcrit) depends on the energy
spectra. The Qcrit of fission neutrons (similar to electron linac produced
Giant-Dipole-Resonance spectrum) was calculated to be 0.15 pico
Coulomb. The physical properties of some important semiconductor
materials are shown in the Table below:
Using equations 1- 4 one can calculate the number SEU induced in a SRAM.
NEUTRON INDUCED NUCLEAR REACTIONS
IN THE MICROCHIP
Nuclear Reaction with Boron (1)
Boron is used as a dopant and
component of the glassification layer:
10B
5
+ 0n1 = 7Li3 + 4He2
(Q = + 2.65 MeV)
(1)
Nuclear Reactions with Silicon (2 & 3)
Silicon is the major building block of
all semiconductor devices:
28Si
14
+ 0n1 = 25Mg12 + 4He2
(Q = - 2.65 MeV)
28Si
14
+ 0n1 = 28Al13 + 1H 1
Q = - 3.85 MeV)
(2)
(3)
NEUTRON INDUCED NUCLEAR REACTIONS
IN THE MICROCHIP (contd.)
Boron-10 (10B5) makes only 19.9% abundance in natural boron. However, due
to very high “exothermic” reaction cross section of 3000 barn for thermal
neutrons, the neutron capture reaction (1) overwhelms the “endothermic” (n,
a) and (n, p) reactions (2 and 3) in Silicon (cross sections ca. 0.1 barn).
The physical properties of the reaction products of 10B(n, a)7Li reaction are
summarised in Table below.
Evidently, due to a higher range (5 micron) in silicon, the alpha particles
(4He) are the main candidate for triggering SEU in the microchip.
NEUTRON IRRADIATION OF SRAM CHIPS
512 kB non-volatile SRAM chips were irradiated with 241Am-Be
neutrons and stray neutrons existing in the TTF 2 tunnel.
(1) 241Am-Be Neutron Irradiation Device
B: Thermal Neutron Shield (Borated Polyethylene)
D: Device under Test (DUT)
H: Table
J1, J2: Jars (16 and 33 cm radius respectively)
P: Stand
S: 241Am-Be Neutron source
T: Tripod (Source holder)
(2) In the TTF 2 (Electron Linac) Tunnel, warm side
C: Cable Duct
E: Electronic Instrument Cabinet
Q: Quadrupole Lens
S: SRAM Chips
W: Catwalk
INTERPRETATION OF EXPERIMENTAL RESULTS
The number of SEU counted after neutron irradiation of the 512 kB SRAM
chips are shown in the Table below:
The normalised SEU counts
of the bare, polyethylenemoderated and shielded with
Borated Polyethylene (PolyBor) sheet are shown in the
next Figure.
The lowest number SEU in the Poly-Bor shielded SRAM chips irradiated at the
Linac reveals the existence of a high number of thermal neutrons in the tunnel.
SUMMARY AND CONCLUSION
Using the physical principle of nuclear reaction we have analysed the
phenomena of Single Event Upset in Static Random Access Memories
(SRAM) set off by neutrons.
We have investigated the SEU initiated in 512 kB SRAM chips by
isotopic neutrons from an 241Am-Be source as well as stray photoneutrons produced by the 450 MeV superconducting electron linac (TTF
2 of DESY) and interpreted the results.
In the TTF2 tunnel the thermal neutron produced by multiple collision of
primary (GDR) Photoneutrons with the containment wall found to be the
main source of triggering the SEU.
The implementation of a 3.5 mm thick borated polyethylene shield
reduced incidence rate of SEU by more than one order of magnitude
The main aim of this investigation is to establish an optimum mitigation
strategy for the reduction of SEU in SRAM and FPGA chips to be used in
the VUV FEL and XFEL facilities of DESY.
THANK YOU FOR YOUR ATTENTION
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