Transcript CS 2204 Fall 2005 - NYU Polytechnic School of Engineering

CS 2204
Lab 8
Experiment 4 - 5
Spring 2008
Digital
Logic and
State Machine Design

Lab 8 Outline
 Presentation

Digital product development overview
 Digital Product Development
• Component selection for a PCB
 TTL LS SSI chip usage
• Component selection for a chip
 Xilinx component usage



Analysis of Block 1 of the term project
A machine playing strategy
Xilinx sequential circuit components
 Individual work

Experiment 4
 Develop the Rightmost Largest Display circuit of the Ppm term
project

Experiment 5
 Develop the BCD up counter in the Random Digit Generation
Subsubblock of the Ppm term project
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 2

Developing a new PCB
1) Development Cycle on Computers
Major error : Redesign
DESIGN
TEST
MODIFY
Major error : Redesign or terminate the project due to TTM
2) Dev. Cycle with off-the-shelf chips
Mount
Test
Modify
Major error : Redesign or terminate the project due to TTM
3) Dev. Cycle on prototype PCB
Fabricate
Test
Modify
PCB
Which chips and how many ?
TEST : Simulating by applying input
combinations, test vectors, may not be
possible. It may be coarse grain simulation
During testing if you see MODIFYING
hardware to optimize it is possible, do that
after you correct logic and timing errors.
Then, test again to see if your minimization
has logic/timing errors
Mount : Chips are mounted on
bread/boards and wired
Test : apply test vectors to the chips
Modify : chip mounting/wiring is changed
and tested or a simple design change is
made on computers, simulated, then FPGAs
are programmed and tested
Fabricate PCB at a fabrication facility,
mount chips and other components
Apply test vectors to the PCB
Modify means chip mounting/wiring is
changed and tested
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 3

Developing a digital product
 A new PCB

Which chips and how many is determined by
 The application (major operations)
 Available chips of the technology chosen
 Besides speed, cost, power, etc. : design goals
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 4

CS2204 components
 Available chips for a new PCB
Use these Generic chips
as much
Lectures, homework, exams
as possible
Flip-flops Popular digital circuits
AND
D
OR
JK
NOT
T
NAND
SR
NOR
…
…
To save time,
space, power.
weight,…
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
High-density chips
Gates
TTL LS chips
Lectures, homework, exams
Gates
AND
OR
NOT
NAND
NOR
…
Flip-flops
D
JK
Popular digital circuits
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 5
CS2204 components
 Available chips for a new PCB
Generic chips
Lectures, homework, exams
Gates
AND
OR
NOT
NAND
NOR
…
Flip-flops Popular digital circuits
D
JK
T
SR
…
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
Use higher density chips
as much as possible
TTL LS chips
Lectures, homework, exams
Gates
AND
OR
NOT
NAND
NOR
…
Flip-flops
D
JK
Try not to use
these SSI chips
Popular digital circuits
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
High-density chips

Page 6

Try not
use SSI chips
TTL LS SSI Chips Used
Thisto
Semester
 They have less than 10 gates according to the A Brief Look at
Semiconductor Technology handout
NAND-Gate Chips
74LS00 4 2-input NAND gates
74LS10 3 3-input NAND gates
74LS20 2 4-input NAND gates
74LS30 1 8-input NAND gate
From ON Semiconductor
LS TTL Data Manual
From Texas Instruments
Digital Logic Data Book
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 7

Try not
use SSI chips
TTL LS SSI Chips Used
Thisto
Semester
 They have less than 10 gates according to the A Brief Look at
Semiconductor Technology handout
NOR-Gate Chips
74LS02 4 2-input NOR gates
74LS27 3 3-input NOR gates
From Texas Instruments
Digital Logic Data Book
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 8

Try not
use SSI chips
TTL LS SSI Chips Used
Thisto
Semester
 They have less than 10 gates according to the A Brief Look at
Semiconductor Technology handout
Inverter-Gate Chips
74LS04 6 inverters
From ON Semiconductor
LS TTL Data Manual
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 9

Try not
use SSI chips
TTL LS SSI Chips Used
Thisto
Semester
 They have less than 10 gates according to the A Brief Look at
Semiconductor Technology handout
AND-Gate Chips
74LS08 4 2-input AND gates
74LS11 3 3-input AND gates
74LS21 2 4-input AND gates
From ON Semiconductor
LS TTL Data Manual
From Texas Instruments
Digital Logic Data Book
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 10

Try not
use SSI chips
TTL LS SSI Chips Used
Thisto
Semester
 They have less than 10 gates according to the A Brief Look at
Semiconductor Technology handout
OR-Gate Chips
74LS32 4 2-input OR gates
From ON Semiconductor
LS TTL Data Manual
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 11

Try not
use SSI chips
TTL LS SSI Chips Used
Thisto
Semester
 They have less than 10 gates according to the A Brief Look at
Semiconductor Technology handout
EX-OR-Gate Chips
74LS86 4 2-input EX-OR gates
From Texas Instruments
Digital Logic Data Book
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 12

Try not
use SSI chips
TTL LS SSI Chips Used
Thisto
Semester
 They have less than 10 gates according to the A Brief Look at
Semiconductor Technology handout
AND-OR-Invert-Gate Chips
74LS51 Dual AOI Network
From Texas Instruments
Digital Logic Data Book
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 13

TTL LS SSI Chips Used
This
Try not
toSemester
use SSI chips
 They have less than 10 gates according to the A
Brief Look at Semiconductor Technology handout
EX-NOR-Gate Chips
74LS266 4 2-input EX-NOR gates
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 14

Try This
not to
use SSI chips
TTL LS SSI Chips Used
Semester
 They have less than 10 gates according to the A Brief Look at
Semiconductor Technology handout
D-FF Chips
74LS74 2 positive-edge triggered D Fs
From ON Semiconductor
LS TTL Data Manual
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 15

Try not
toSemester
use SSI chips
TTL LS SSI Chips Used
This
 They have less than 10 gates according to the A Brief Look at
Semiconductor Technology handout
J-K-FF Chips
74LS112 2 negative-edge triggered J-K Fs
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 16
Implementing a Combinational Circuit on a New PCB
 By using TTL LS SSI chips with
OR,
NOT,…
gates
Try AND,
not to
use
SSI chips


a
The 2-to-1 MUX
Which TTL components ?
NOT
b
AND
OR
c
a
AND
We need :
1 inverter
2 2-input AND gates
1 2-input OR gate
y(a, b, c) = a.b + a.c
TTL LS SSI Chip Usage ?
1 74LS04 with 6 inverters, 5 inverters unused
1 74LS08 with 4 2-input AND gates, 2 gates unused
1 74LS32 with 4 2-input OR gates, 3 gates unused
Total : 3 chips used, 10 gates unused
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 17

Implementing a Combinational Circuit on a New PCB
 The 2-to-1 MUX

Try not to use SSI chips to implement combinational circuits
 Use higher density chips : 74LS157 TTL LS MSI chip : 4 2-to-1 MUXes
• One chip has four 2-to-1 MUXes !
Which TTL components ?
0 bc 0 0 00 0 0
1 74LS157 4-bit 2-to-1 MUX
Total : 1 chip used, 0 gates unused
a
y
From ON Semiconductor LS TTL Data Manual
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 18

Implementing a Combinational Circuit on a New PCB
Try not
toOR,
use NOT,…
SSI chips
 By using TTL LS SSI chips with
AND,
gates
TTL LS SSI Chip Usage ?
a
We need :
Which TTL components ?
2 inverters
5 2-input AND gates
No TTL chip with
1 5-input OR gate
5-input OR gates
ab
b
a
ad
d
z
d
OR
a
OR
ac
c
c
c
cd
d
b
OR
ab + ad + ac + c d + b c
bc
c
2-bit Unsigned
Binary Comparator
From Handout 5
Implement it with 4
2-input OR gates
OR
We need :
2 inverters
5 2-input AND gates
4 2-input OR gates
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 19

Implementing a Combinational Circuit on a New PCB
Try not
toOR,
use NOT,…
SSI chips
 By using TTL LS SSI chips with
AND,
gates
TTL LS SSI Chip Usage ?
a
ab
Which TTL components ?
b
a
ad
d
z
d
a
ac
c
ab + ad + ac + c d + b c
c
c
We need :
2 inverters
5 2-input AND gates
4 2-input OR gates
cd
d
b
bc
c
2-bit Unsigned
Binary Comparator
From Handout 5
1 74LS04 with 6 inverters, 4 inverters unused
2 74LS08 with 4 2-input AND gates, 3 gates unused
1 74LS32 with 4 2-input OR gates, 0 gates unused
Total : 4 chips used, 7 gates unused
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 20

Implementing a Combinational Circuit on a New PCB
 2-bit Unsigned Binary Comparator

Try not to use SSI chips to implement combinational circuits
 Use higher density chips : 74LS85 TTL MSI chip : a 4-bit Unsigned
Binary comparator
• We also need a 74LS32 OR-gate SSI chip !
• Two chips used !
a
ab
b
a
ad
d
z
d
a
ac
c
c
c
cd
d
b
bc
c
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 21

Implementing a Combinational Circuit on a New PCB
 2-bit Unsigned Binary Comparator

Try not to use SSI chips to implement combinational circuits
b a 0 0 d c 0 0
0
0
1
74LS85
z
1 74LS85 4-bit Unsigned Comparator
1 74LS32 with 4 2-input OR gates, 3 gates unused
Total : 2 chips used, 3 gates unused
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 22
Implementing a Sequential Circuit on a New PCB

 By using TTL LS SSI chips with
D, J-K,
AND,
NOT,… gates
Try not
to use
SSIOR,
chips
TTL LS SSI Chip Usage ?
y1
x
J
y0
y1
Q
C
K
clock
y2
x
y0
J
x
y0
y0
Q
C
y2
x
y0
Q
y1
K
x
clock
y2
Least significant FF
x
y2
J
y0
x
y1
y2
K
1 inverter
4 2-input AND gates
6 3-input AND gates
1 4-input AND gate
4 2-input OR gates
2 3-input OR gates
3 J-K FFs
Q
y2
C
Which components ?
y0
We need :
most significant FF
y1
Q
y0
y1
clock
y2
Q
x
y2
y2
y0
y1
y2
x
x
z
x
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 23

Implementing a Sequential Circuit on a New PCB
 By using TTL LS SSI chips with
D, J-K,
AND,
OR,
NOT,… gates
Try not
to use
SSI
chips
TTL LS SSI Chip Usage ?
Which components ?
There is no positive-edge
triggered J-K FF chip ! We
need one more inverter to
invert the clock
There is no 3-input OR-gate chip !
We implement it with 2-input OR gates
OR
OR
OR
We need :
1 inverter
4 2-input AND gates
6 3-input AND gates
1 4-input AND gate
4 2-input OR gates
2 3-input OR gates
3 positive-edge triggered J-K FFs
We need :
2 inverters
4 2-input AND gates
6 3-input AND gates
1 4-input AND gate
8 2-input OR gates
3 negative-edge triggered J-K FFs
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 24

Implementing a Sequential Circuit on a New PCB
TryD,
not
toAND,
use SSI
chips gates
 By using TTL LS SSI chips with
J-K,
OR, NOT,…
We need :
1 inverter
4 2-input AND gates
Here there
6 3-input AND gates
We have to
1 4-input AND gate
4 2-input OR gates
2 3-input OR gates
3 positive-edge triggered J-K FFs
is no choice !
use SSI chips !
1 74LS04 with 6 inverters, 4 inverters unused
1 74LS08 with 4 2-input AND gates, 0 gates unused
2 74LS11 with 3 3-input AND gates, 0 gates unused
1 74LS21 with 2 4-input AND gates, 1 gate unused
2 74LS32 with 4 2-input OR gates, 0 gates unused
2 74LS112 with 2 negative-edge triggered J-K FFs, 1 FF unused
Total : 9 chips used, 5 gates and 1 FF unused
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 25

Developing a new chip
1) Development Cycle on Computers
Major error : Redesign
DESIGN
TEST
MODIFY
Major error : Redesign or terminate the project due to TTM
2) Development Cycle with FPGA chips
Mount
Test
Modify
Major error : Redesign or terminate the project due to TTM
3) Development Cycle on prototype chip
Fabricate
Test
Which components and how many ?
TEST : applying input combinations,
test vectors, and simulating
During testing If you see MODIFYING
hardware to optimize it is possible, do
that after you correct logic and timing
errors. Then, test again to see if your
minimization has logic/timing errors
Mount : FPGAs are mounted on
bread/boards, wired and programmed
Test : apply test vectors to FPGAs
Modify : either FPGA mounting/wiring
is changed or a simple design change is
made on computers, simulated, then
FPGAs are programmed and tested
Fabricate chip by sending a GDSII file
to a fabrication facility : tape out
Apply test vectors to the chip
Chip
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 26

Developing a digital product
 A new chip

Which gates/FFs and how many is determined by
 The application (major operations)
 Available components of the technology chosen
 Besides speed, cost, power, etc. : design goals
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 27

CS2204 Components
 Available components for a new chip
Use these Generic components
Lectures, homework, exams
as much
as possible
Flip-flops Popular digital circuits
AND
D
OR
JK
NOT
T
NAND
SR
NOR
…
…
To save time,
space, power.
weight,…
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
High-density circuits
Gates
Xilinx components
Labs
Gates
AND
OR
NOT
NAND
NOR
…
Flip-flops
D
JK
Popular digital circuits
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register
…
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 28

Implementing a Combinational Circuit on a New Chip
 By using generic components that are AND, OR, NOT,…

a
The 2-to-1 MUX
Which components ?
1 inverter
2 2-input AND gates
1 2-input OR gate
NOT
b
AND
OR
c
a
AND
Total : 4 gates used
y(a, b, c) = a.b + a.c
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 29

Implementing a Combinational Circuit on a New Chip
 By using generic components that are AND, OR, NOT,…
a
ab
Which components ?
b
a
ad
d
z
d
a
ac
c
ab + ad + ac + c d + b c
c
c
2 inverters
5 2-input AND gates
1 5-input OR gate
Total : 8 gates used
cd
d
b
bc
c
2-bit Unsigned Binary Comparator
From Handout 5
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 30
Implementing a Sequential Circuit on a New Chip

 By using generic components that are D, J-K, AND, OR, NOT,…
The sequence detector from Handout 9

y1
x
J
y0
y1
Q
y2
Q
C
K
clock
y2
x
y0
J
x
y0
y0
y2
x
y0
Q
C
K
x
Q
y1
clock
y2
Least significant FF
x
y2
J
y0
x
y1
y2
K
C
Which components ?
y0
1 inverter
4 2-input AND gates
6 3-input AND gates
1 4-input AND gate
4 2-input OR gates
2 3-input OR gates
3 J-K FFs
most significant FF
Total : 21 components used
y1
Q
y0
y1
clock
y2
Q
x
y2
y2
y0
y1
y2
x
x
z
x
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 31
CS2204 Components
 Available components for a new chip
Generic components
Lectures, homework, exams
Gates Flip-flops
AND
OR
NOT
NAND
NOR…
D
JK
T
SR
Popular digital circuits
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register…
Xilinx components
Labs
Lab design
Use Xilinx macros
as much as possible
Gates Flip-flops Popular digital circuits
AND
OR
NOT
NAND
NOR…
D
T
JK
Try not to use
these components
ADDer
Comparator
Multiplexer
DeMux
Decoder
Encoder
ALU
Counter
Register…
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
High-density chips

Page 32

Implementing a Combinational Circuit on a New Chip
 By using Xilinx components that are AND, OR, NOT,…

a
The 2-to-1 MUX
1 inverter, INV
2 2-input AND gates, AND2
1 2-input OR gate, OR2
NOT
b
Total : 4 gates used
AND
OR
c
a
AND
y(a, b, c) = a.b + a.c
Which Xilinx components ?
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 33

Implementing a Combinational Circuit on a New
Chip
 By using Xilinx components that are AND, OR, NOT,…

The 2-to-1 MUX
Xilinx already has 2-to-1 MUXes
Use them
Do not design your own 2-to-1 MUX
a
NOT
b
AND
OR
c
a
AND
y(a, b, c) = a.b + a.c
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 34

Implementing a Combinational Circuit on a New Chip
 The 2-to-1 MUX

Xilinx already has 2-to-1 MUX macros
 M2_1
Which Xilinx components ?
1 Xilinx M2_1 MUX
Total : 1 component used
a
NOT
b
AND
OR
c
a
AND
y(a, b, c) = a.b + a.c
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 35

Implementing a Combinational Circuit on a New Chip
 By using Xilinx components that are AND, OR, NOT,…
a
ab
b
a
Which Xilinx components ?
ad
d
z
d
a
ac
c
ab + ad + ac + c d + b c
c
c
2 inverters, INV
5 2-input AND gates, AND2
1 5-input OR gate, OR2
Total : 8 gates used
cd
d
b
bc
c
2-bit Unsigned Binary Comparator
From Handout 5
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 36

Implementing a Combinational Circuit on a New Chip
 By using Xilinx components that are AND, OR, NOT,…
2-bit
Unsigned Binary Comparator
Use them
Xilinx already has Comparators
You need an extra OR gate besides the comparator
Do not design your own Comparator
a
ab
b
a
ad
d
z
d
a
ac
c
c
c
cd
d
b
bc
c
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 37

Implementing a Combinational Circuit on a New Chip
 2-bit Unsigned Binary Comparator

By using Xilinx comparators
1 Xilinx 74_L85 Comparator, X74_L85
1 Xilinx 2-input OR gate, OR2
Total : 2 components used
Which Xilinx components ?
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 38
Implementing a Sequential Circuit on a New Chip

 By using Xilinx components that are D, J-K, AND, OR, NOT,…
 The sequence detector from Handout 9
y1
Which components ?
y0
most significant FF
x
J
y0
y1
Q
y2
Q
C
K
clock
y2
x
y0
J
x
y0
y0
Total : 21 components used
y2
x
y0
Q
C
K
x
Q
y1
1 inverter, INV
4 2-input AND gates, AND2
6 3-input AND gates, AND3
1 4-input AND gate, AND4
4 2-input OR gates, OR2
2 3-input OR gates, OR3
3 positive-edge triggered J-K FFs, FJKC
clock
y2
y1
y2
Least significant FF
x
y2
J
y0
x
y1
y2
K
C
Q
y0
Q
x
y1
y2
clock
y2
y0
y1
y2
x
x
z
x
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 39

Implementing a Combinational Circuit on a New Chip
 By using Xilinx components that are D, J-K, AND, OR, NOT,…
 The sequence detector from Handout 9
Xilinx does not have this sequence detector
We have to design our own sequence detector
y1
y0
most significant FF
x
J
y0
y1
Q
y2
Q
C
K
clock
y2
The design with
21 components
is implemented
x
y0
J
x
y0
y0
y2
x
y0
Q
C
K
x
Q
y1
y1
clock
y2
Least significant FF
x
y2
J
y0
x
y1
y2
K
C
y1
Q
y0
x
y2
y0
Q
y1
y2
y2
y2
x
x
z
x
clock
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 40

Analysis of the Term Project
 The term project black-box view
 The term project operation diagram
 The term project black box partitioning
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 41

The Term Project, Ppm
 The black-box view
From the input devices
13
From page 2 of the Term Project Handout
19
Ppm
To the output devices
Figure 1. The Ppm black box view.

Ppm is sequential (not combinational)
 A large number of FFs are used !

Ppm is a digital system
 We need to partition the Ppm based on major operations
• We have to obtain the operation diagram
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 42
From page 8 of the Term Project Handout
LD6-LD8 on the
FPGA board
show the
current state
Ppm
Input/output
relationship
Ppm
operation
diagram
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 43

The Ppm Term Project
 Ppm is a digital system !
From the input devices
10
19
Ppm
To the output devices
Figure 1. The Ppm black box view.
 The Ppm term project partitioning

First partitioning of the digital system
 Control Unit
 Data Unit

core
Second partitioning (Data Unit partitioning)





Interfacing to the input/output devices core
Handling human player’s play core
Controlling display operations based on game rules core
Calculating new player points core
Determining the machine player play non-core
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 44

The Ppm Digital System Partitioning
M1
M2
From page 9 of the Term Project Handout
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 45

The term project black box partitioning
• Six schematics for six blocks
•
•
•
•
Block 1 : Control Unit : ppm1.sch schematic file
Block 2 : Input/Output : ppm2.sch schematic file
Block 3 : Human Play : ppm3.sch schematic file
Block 4 : Play Check : ppm4.sch schematic file
• Experiment 1 is on a circuit in this block
•
•
Block 5 : Points Calculation : ppm5.sch schematic
file
Block 6 : Machine Play : ppm6.sch schematic file
• The Machine Play Block uses all other blocks except the
Human Play Block
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 46

Digital Systems
 A digital system performs microoperations
 A digital system consists of digital circuits

A digital system consists of
 A data unit (datapath)

It performs microoperations
 A control unit

It controls the datapath
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 47

Digital Systems
 This first partitioning of a digital system is universal
Other digital systems/
Input/Output devices
Registers
ALUs
buses
control signals
status signals
Sequencer
Data Unit
(Datapath)
Control Unit
Figure 7. A large scale view of a digital system.
 A microprocessor is a digital system
 An iPhone is a digital system
 A computer is a collection of digital systems
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 48

Digital Systems
 The data unit has registers, ALUs and buses
to perform microoperations
Registers keep (store) data (operands and results)
 Arithmetic Logic Units (ALUs) perform additions,
subtractions, multiplications, ANDS, ORs, etc.
 Buses interconnect registers and ALUs

CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 49

Digital Systems
 The Control Unit (Sequencer)

The control unit determines the sequence of
microoperations based on the status signals
 The control unit goes through states
• In each state, it enables the microoperations of that state
to happen in the data unit based on the status signals
► Microoperations must start at the right time with correct
inputs and end at the right time with correct outputs
 We should not lose data and we should not use old data
► Glitches, gate delays must be accounted for
 When we design it, we account for every possible gate delay
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 50

Digital Systems
 The Control Unit (Sequencer)


The state register indicates the current state
Logic to generate the control signals and the next state
more irregular than the Data Unit
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 51

Digital Systems
 The Control Unit (Sequencer) design

Hardwiring vs microprogramming
Gate/FF networks = random logic = irregular
Memory bits generate control signals and NS
Highly
regular
but slower
Not as
regular
as the
datapath
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 52

Digital Systems
 The Control Unit (Sequencer) design

First partitioning on the Control Unit
 Control Signal generation Subblock
 Next State Generation Subblock
Often a decoder is
used to generate
the control and
next state signals
Often a counter is
used instead of a
register since we
trace the states
sequentially
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 53

The Ppm Control Unit
 Block 1, the Control Unit (the sequencer)
16
Block 1
18
 It controls the Data Unit

It determines the sequence of microoperations
 Which microoperation happens when
How can we implement the block ?
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 54

The Ppm Control Unit

Block 1, the Control Unit (the sequencer)

The control unit determines the sequence of
microoperations based on the status signals



Implemented by using the FSM technique
Uses hardwiring
• Gate networks generate control signals
Partitioned into
• Control Signal generation Subblock
• Next State Generation Subblock
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 55

The Ppm Control Unit
 Block 1, the Control Unit (the sequencer)
Control
Signal
Generation
Subblock
Control
signals
Next
State
Generation
Subblock
CounterDecoder
combination
to keep track
of the current
state
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 56

A Machine Player Strategy
Largest reward = 0 ?
N
Y
Player 1 does not have (64) 10 or more
points & there is a position with a zero
& RD is not zero
N
Skip
Y
Player 1 does not have (64)10 or more
points & the largest reward is less than (64)10
N
Play on the
(rightmost)
largest
reward
position
(directly
if equal)
(Action 0)
Y
Play on the
(rightmost)
largest
position
(directly
if equal)
(Action 1)
Play on the
(rightmost)
zero position
directly
(if equal)
(Action 2)
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 57

A Machine Player Strategy
 Its Implementation
Largest reward = 0 ?
N
Y
Player 1 does not have (64) 10 or more
points & there is a position with a zero
& RD is not zero
N
Skip
Y
Player 1 does not have (64)10 or more
points & the largest reward is less than (64)10
N
Play on the
(rightmost)
largest
reward
position
(directly
if equal)
(Action 0)
Y
Play on the
(rightmost)
largest
position
(directly
if equal)
(Action 1)
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Play on the
(rightmost)
zero position
directly
(if equal)
(Action 2)
Page 58

Xilinx FFs, Registers, Counters
 Many do not have direct set and direct clear
inputs together

To avoid cases where both are active
 They have either

A direct set input
 Or

A direct clear input
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 59

Xilinx FFs, Registers, Counters
 Direct set and direct clear inputs

Asynchronous
 As we studied in class
• If the direct input is active, it affects the output immediately
 The name of the FF, register, counter has a
• “C” near the end if it is the direct clear input
► FDC : a D FF with an asynchronous direct clear input
• “P” near the end if it is the direct set (preset) input
► FDP : a D FF with an asynchronous direct set input
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 60

Xilinx FFs, Registers, Counters
 Direct set and direct clear inputs

Synchronous
 If the direct input is active, it affect the output when there is
the active clock edge
 The name of the FF, register, counter has an
• “R” near the end if it is the direct clear input
► FDR : a D FF with a synchronous direct clear input
• “S” near the end if it is the direct clear input
► FDS : a D FF with a synchronous set input
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 61

Xilinx FFs, Registers, Counters
 Some of them have an additional input

Clock Enable (CE)
 The name of the FF, register, counter ends with an “E”
 It controls the clock input
• If it is 1, the clock input gets the clock signal
► It can be clocked (stored)
• If it is 0, the clock input gets 0
► It cannot be clocked (cannot be stored)
 FDCE : A D FF with an asynchronous direct clear input
and a clock enable input
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 62

Xilinx FFs, Registers, Counters
 Clock Enable (CE)

FDCE : A D FF with an asynchronous direct clear input and a
clock enable input
CLR
CE
D
C
1
0
0
0
0
X
1
1
1
0
X
0
1
X
X
X
0
X
Q
0 (Store 0)
0 (Store 0)
1 (Store 1)
NS
NS
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 63

Xilinx FFs, Registers, Counters
 Clock Enable (CE)

The clock enable is often connected the “Store” signal
CE is equivalent to
a
Storey0
Clock
Reset
y0
a
D
Storey0
Q
y0
C
Clock
CLR
Reset
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 64
Q/A
Do not leave the lab before your partners finish
► Help your partners complete today’s project
Read slides starting at the end on term project, Project
Manager, schematic design and other related topics
Continue reading the Term Project handout
Think about the machine player strategy
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 65

Today’s Individual Xilinx Work
 We will continue to study (analyze) the term project


We will use discussions in class Lab 7 notes to implement
Macro 2 (M2) of Block 6 : Experiment 4
We will use our knowledge of counters to modify a portion of
a term project schematic
 We will replace a 4-bit Xilinx BCD up counter (Divide-by-10 or
Modulo-10 counter) with our own circuits : Experiment 5
 Help your partners complete today’s project
 We will continue reading the Term Project handout

Relate each term project (sub)block in the Term Project
handout to the Ppm schematic
 Study Ppm (sub)blocks by performing simulations
 Read slides at the end to learn more about the term
project, Project Manager, schematic design and
other related topics
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 66

Today’s Individual Xilinx Lab Work
1. Copy the exp3 folder and paste it in the
cs2204 folder as the exp4 folder

We will experiment with the Ppm schematics
2. Open the Ppm project in exp4
3. Look at the six Ppm schematics



If you copy a project completely as we did and then open
its schematics, the schematics will be all Non-Project
Therefore, close all these schematics and close the
schematics window
Then, open the schematics one by one on the Project
Manager window, by double clicking on the schematic name
on the upper left side
4. Place your team info on the schematics on
schematic 1 : ppm1.sch
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 67

Today’s Individual Xilinx Lab Work
5. Save schematic 1
6. Switch to schematic 6
7. Zoom into the lower right area, containing
M2
8. There is a custom macro designed by the
professor


It has two outputs that indicate the number of
the rightmost largest display position
See ppm6.sch on the next slide
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 68
Today’s Individual Xilinx Lab Work


Ppm Schematic 6
Macro 2
M2
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 69

Today’s Individual Xilinx Lab Work
9. Analyze the macro to determine how it is
used

See the correspondence between the classroom
discussion and M2 inputs and outputs



Determine which inputs are for display 0, which inputs
are for display 1, etc.
Determine which output is “Y1” and which output is “Y0”
Do a Hierarchy Push and notice that its
implementation cannot be shown by Xilinx

A comment on the bottom of the schematic sheet reads
“Symbol is a primitive cell”
10. Perform functional simulations on this macro

Use also your notes that cover the discussion in
the classroom
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 70

Today’s Individual Xilinx Lab Work
11. Search for the inputs and outputs of the
macro by clicking on the Query window
button on top of the schematic sheet
In the Signal/Bus mode of the SC Query/Find
window that will pop up
Determine which components generate the inputs

DISP0, DISP1, DISP2, DISP3,…, DISP15
Determine which components use outputs

LRGDISPPOS1 and LRGDISPPOS0
12. Delete the macro : M2 in schematic 6


Do not delete the wires
Save schematic 6, ppm6.sch

See modified ppm6.sch on the next slide
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 71
Today’s Individual Xilinx Lab Work


Ppm Schematic 6
Macro 2,
M2
deleted
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 72

Today’s Individual Xilinx Lab Work
13.
14.
Switch to the Human Play Block, Block 3 or ppm3.sch
Draw the schematic of the macro on the lower right side in
schematic 3 by using classroom and Lab 7 discussions and your design

You will implement the LRGDISPPOS1 and LRGDISPPOS0 outputs by using as
many Xilinx design blocks as possible and as few gates as possible







Note that what is discussed in the presentation must be followd where we try
to use as many available components as possible

M2 uses three Xilinx comparators, two Xilinx multiplexers and a few gates

Note that what is learned in designing M1 can be used for M2
You will use the Symbols toolbox button on the leftmost side (or F3) to
get the component list
You will use the Draw wires button on the leftmost side (or F4) to draw
wires
To rotate components right press ctrl-r
To rotate components left, press ctrl-l
Note, wires cannot be rotated

But, by pulling from one end of a wire, it can be rotated !

Label the gates starting at U324
Label the wires (inputs and outputs) based on your analysis in part (9)
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 73

Today’s Individual Xilinx Lab Work
14. Draw the schematic of the macro on the
lower right side in schematic 3 by using
classroom discussions and your design
In the Instance mode of the SC Query/Find
window that will pop up
Determine that there is no component labeled U324
and above
Label the components starting at U324
Save schematic 6, ppm6.sch
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 74

Today’s Individual Xilinx Lab Work
15. Perform an Integrity Test to check for
errors

Integrity tests do not catch all the errors

That is why after the Integrity tests we have to
perform
• Functional simulations
• Xilinx IMPLEMENTATIONs
• Timing simulations
16. Perform functional simulations on this macro
in schematic 3 to verify that it is working

Use the truth table you have developed to test a
portion of M2
Make sure the circuit is beautified and the
schematic is saved again
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 75

Today’s Individual Xilinx Lab Work
17. Do a Xilinx IMPLEMENTATION

Make sure there are no errors


Make sure the IMPLEMENTATION options are
changed so that a better IMPLEMENTATION is done
Read the Implementation Log File to confirm
that

The number of warnings 26
• These warning are OK, we can continue
• Note that there are 26 warnings not 25 as it was
the case in the previous experiment since a wire in
Block 5 is not used
WARNING:NgdBuild:454 - logical net '$Net00202_' has no load
•
This wire is the wire that connected the unused
data inputs of the Xilinx 4-bit ADDer to GND in
Block 5
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 76

Today’s Individual Xilinx Lab Work
17. Do a Xilinx IMPLEMENTATION

Read the Implementation Log File to see that

The FPGA chip utilization is 98%
•
The Xilinx IMPLEMENTATION maps the design to 191 to
193 CLBs, hence 97% to 98% utilization, after an
IMPLEMENTATION, a feature peculiar to FPGA testing
 The conversion of the schematic to the bit file is
“randomized” to have a better mapping of the logic to
CLBs, but it leads to this situation
 That is why we fabricate the prototype chip before we mass
produce it to test the design one more time to make sure
the design is correct
 Nevertheless, the utilization is high since two gate networks
implement a full adder and this implementation is worse than
the Xilinx implementation
 That is why it is better that we use Xilinx components if
they are available
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 77

Today’s Individual Xilinx Lab Work
17. Do a Xilinx IMPLEMENTATION

The Project Manager window looks like this after the
IMPLEMENTATION is completed successfully :
Make sure the options
for IMPLEMENTATION
are “High Effort” “50”
and “5”
The checkmark for
IMPLEMENTATION
can be delayed a few
minutes sometimes
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 78

Today’s Individual Xilinx Lab Work
18. Do you think there is a possibility of a glitch
by the full adder circuit ?



If yes, which output(s) would have the glitch ?
Which input combination pairs would generate
the glitch ?
Observe the glitch and show it to the TA
19. Download the Ppm project to the FPGA chip
and play the game and to verify that the
schematic works correctly
If it does not work, inspect your circuit in Block
3 and correct your circuit
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 79

Today’s Individual Xilinx Lab Work
1. Copy the termproject folder and paste it in
the cs2204 folder as the exp5 folder

We will experiment with the Ppm schematics
2. Open the Ppm project in exp5
3. Look at the six Ppm schematics



If you copy a project completely as we did and then open
its schematics, the schematics will be all Non-Project
Therefore, close all these schematics and close the
schematics window
Then, open the schematics one by one on the Project
Manager window, by double clicking on the schematic name
on the upper left side
4. Place your team info on the schematics on
schematic 1 : ppm1.sch
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 80

Today’s Individual Xilinx Lab Work
5. Save schematic 1
6. Switch to schematic 4
7. Zoom into the upper right area, containing the
Random Digit Generation Subsubblock
8. There is a Xilinx macro (a Xilinx Design Block, XDB)
with U117

A BCD Up Counter, CD4CE, in the subsubblock




It counts up 0 to 9, inclusive
• Its clock is always enabled (CE = 1)
• Its direct clear input is always inactive (CLR = 0)
It implements the BCD Up counter similar to the modulo-12
counter implemented in class
• We used a TTL LS chip : 74LS169
See ppm4.sch on the next slide
See the subsubblock in more detail on the slide that
follows
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 81
Today’s Individual Xilinx Lab Work


Ppm Schematic 4
Xilinx
BCD Up
Counter
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 82
Today’s Individual Xilinx Lab Work


Ppm Schematic 4
P2RD
P1RD
RD
Xilinx 4-bit registers
which are stored 3
random digits when
Grd (Get Random
Digit) is raised to
1 by the control
unit when BTN1
or BTN2 is pressed
Xilinx BCD
Up Counter
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 83

Today’s Individual Xilinx Lab Work
9. Analyze the BCD up counter to determine how its
inputs and outputs are used

It counts up at the rate of Rdclk (Random digit clock)


Rdclk is generated in the Timing Subblock of schematic 2
 It is derived from Q0 which is one of the outputs of a
16-bit Xilinx binary counter, CB16CE, U64
 Q0 has the frequency of 192 Hz
Three outputs of the counter are stored on a Xilinx 4-bit
register
 The counter value is stored as the random digit when Grd
(Get random digit) is 1
 The rightmost output of the counter is not stored on the
register !
 If this output is connected to the register, the random
digit is always odd (1, 3, 5, 7 and 9)
 It is a problem of the Xilinx software and so to get
around it the register is connected Q7 from U64 in
schematic 2
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 84

Today’s Individual Xilinx Lab Work
9. Analyze the BCD up counter to determine
how its inputs and outputs are used

See the correspondence between this circuit and
your class notes


The Xilinx counter is an Up counter and so does not
have the U/D input
Its internal design is for BCD counting and so no
external gate is needed
• Do a Hierarchy Push and see how it is implemented
by Xilinx
• Do a Hierarchy Pop to close the internal circuit
schematic
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 85

Today’s Individual Xilinx Lab Work
10. Perform functional simulations on the Xilinx
BCD counter

In order to simulate, we need to name the
outputs of the Xilinx counter



Output Q0 does not have a wire connected
• Connect a short wire to the output and name it
RDC0 where RDC stands for “Random Digit Counter”
Name the other three output as RDC1, RDC2 and RDC3
See the next slide for the outputs of the counter
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 86
Today’s Individual Xilinx Lab Work


Ppm Schematic 4
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 87

Today’s Individual Xilinx Lab Work
10. Perform functional simulations on the Xilinx
BCD counter

When you do the simulations




See slide 129 to learn how to supply the periodic clock
signal
You can start with any initial value (initial count), since
it is a counter,
Apply at least 13-14 clock cycles to observe the outputs
so that they cycle around
See the next slide that shows the simulation for 14
clock periods
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 88
Today’s Individual Xilinx Lab Work


The simulation window for the Xilinx BCD Counter
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 89

Today’s Individual Xilinx Lab Work
11. Search for the inputs and outputs of the Counter
by clicking on the Query window button on top of
the schematic sheet to confirm your findings in
part (9)
In the Signal/Bus mode of the SC Query/Find window that
will pop up
Determine the component that generates the input
 Rdclk
Determine the components that use outputs
 RDC1, RDC2 and RDC3
12. Delete the Xilinx BCD Up Counter in schematic 4


Do not delete the wires
Save schematic 4, ppm4.sch

See modified ppm4.sch on the next slide
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 90
Today’s Individual Xilinx Lab Work


Ppm Schematic 4
Xilinx
BCD
Counter
deleted
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 91

Today’s Individual Xilinx Lab Work
13. Switch to the Human Play Block, Block 3 or
ppm3.sch
14. Draw the gate network of the BCD Up Counter by
using your class notes in the upper mid area in
schematic 3

On paper, design the circuit by using your class notes

You will use a NAND gate to detect number 9 in Unsigned
binary (1001)
•
In class, number 12 in Unsigned Binary (1100) is detected
•
In class, we loaded (0001) to the counter
•
Use, the closest one, X74_161 which is equivalent to the TTL
74LS161 4-bit Up counter chip
► It is an Up Counter and so does not have the U/D input
► It has an extra input : asynchronous direct clear

You will load (0000) to the counter

Xilinx does not have the equivalent of the 74LS169 chip used
in class
 It is not needed and so connect 1 permanently
► Its ENP and ENT inputs allow counting up
 They are not needed and so connect 1 to them permanently
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 92

Today’s Individual Xilinx Lab Work
14. Draw the gate network of the BCD Up Counter by
using your class notes in the upper mid area in
schematic 3

After the paper design is complete, move the design to the
computer



Place the components on the screen based on your paper
design
Wire the components based on your paper design
Label the wires (inputs and outputs)
• Name the components of the BCD Up Counter from left
to right and top to bottom starting at U332
► The last component label is U333


Save schematic 3, ppm3.sch
See modified ppm3.sch on the next two slides


First the BCD counter circuit
Then, the modified ppm3.sch
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 93
Today’s Individual Xilinx Lab Work


The BCD counter circuit in ppm3.sch
BCD Up Counter
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 94
Today’s Individual Xilinx Lab Work


Ppm Schematic 3
BCD Up Counter
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 95

Today’s Individual Xilinx Lab Work
15. Perform an integrity test to check for errors

Integrity tests do not catch all the errors

That is why after the Integrity tests we have to perform
• Functional simulations
• Xilinx IMPLEMENTATIONs
• Timing simulations
16. Perform functional simulations on this BCD Up
Counter in schematic 3 to verify that it is working


See slide 129 about supplying the periodic clock signal
Make sure the circuit is beautified and the schematic is
saved again
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 96

Today’s Individual Xilinx Lab Work
17. Do a Xilinx IMPLEMENTATION

Make sure there are no errors


Make sure the IMPLEMENTATION options are changed so
that a better IMPLEMENTATION is done
Read the Implementation Log File to confirm that

The number of warnings 26
• These warning are OK, we can continue
• Note that there are 26 warnings not 24 as it is the case
with the term project since two wires in Block 4 are not
used
WARNING:NgdBuild:454 - logical net '$Net00619_' has no load
WARNING:NgdBuild:454 - logical net '$Net00620_' has no load
•
These wires are the wires that connected the CE and CLR
inputs of the Xilinx BCD counter to VCC and GND in Block
4, respectively
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 97

Today’s Individual Xilinx Lab Work
17. Do a Xilinx IMPLEMENTATION

Read the Implementation Log File to see that

The FPGA chip utilization is 97%
•
The Xilinx IMPLEMENTATION maps the design to 190 to 191
CLBs, hence 96% to 97% utilization, after an
IMPLEMENTATION, a feature peculiar to FPGA testing
 The conversion of the schematic to the bit file is
“randomized” to have a better mapping of the logic to
CLBs, but it leads to this situation
 That is why we fabricate the prototype chip before we mass
produce it to test the design one more time to make sure
the design is correct
 Nevertheless, the utilization is high since two gate networks
implement a full adder and this implementation is worse than
the Xilinx implementation
 That is why it is better that we use Xilinx components if
they are available
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 98

Today’s Individual Xilinx Lab Work
17. Do a Xilinx IMPLEMENTATION

The Project Manager window looks like this after the
IMPLEMENTATION is completed successfully :
Make sure the options
for IMPLEMENTATION
are “High Effort” “50”
and “5”
The checkmark for
IMPLEMENTATION
can be delayed a few
minutes sometimes
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 99

Today’s Individual Xilinx Lab Work
18. Do you think there is a possibility of a glitch ?



If yes, which output(s) would have the glitch ?
Which input combination pairs would generate the glitch ?
Observe the glitch and show it to the TA
19. Download the Ppm project to the FPGA chip and
play the game and to verify that the schematic
works correctly

If it does not work, inspect your circuit in Block 3 and
correct your circuit
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 100

Today’s Individual Xilinx Lab Work
20. Help your partners complete today’s project
21. Continue reading the Term Project handout

Relate each term project (sub)block in the Term Project
handout to the Ppm schematic


Study Ppm (sub)blocks by performing simulations
Play the other two versions of the term project to
refresh your memory
•
•
Ppm human vs. human : ppmhvsh
Ppm machine vs. machine : ppmmvsm
22. Read slides at the end to learn more about the
term project, Project Manager, schematic design
and other related topics
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 101

Understand Critical Wires
RD : 4 bits
 The random digit
R1D : 4 bits
Next random digit
R2D : 4 bits
The random digit after next random digit
P1add, TRD : 4 bits
Altogether they form a random digit manually input to the machine player to
test it
In order to input it, one of SW1 – SW4 must be 1
DISP : 16 bits
 They represent the four position displays
 In Hex
 DISP15-DISP12 : the leftmost position display, PD3
 DISP11-DISP8 : position display PD2, etc
TDISP : 16 bits
Next display bits after the current random digit is played
SELTPD : 4 bits
Selects between DISP and TDISP to add the current or next random digit
If it is 0, it selects DISP, otherwise TDISP
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 102

Understand Critical Wires
TADDDISP : 16 bits
The result of selection between DISP and TDISP
NPDISP : 16 bits
 TADDDISP digits plus RD
NDISP : 16 bits
 New DISP bits
 In Hex
BRWD : 4 bits
 Basic reward
 In Hex
 The digit played and also minimum points earned
Brwdeqz : 1 bit
 BRWD is zero when it is 1
PDPRD : 4 bits
 Display overflow bits after addition
Pdprd : 1 bit
The display overflow bit of the position played
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 103

Understand Critical Wires
Selplyr : 1 bit
 The current player
 If it is 0, it is the human player, otherwise, it is the machine
player
P1SEL : 4 bits
 The position played by the human player
P2SEL : 4 bits
 The position played by the machine player
PSEL : 4 bits
 Position Select bits of current player
ENCPSEL : 2 bits
 The number of the position played
EQ : 4 bits
 The equality of the four displays to the digit played
NSD : 2 bits
 The number of similar digits, i.e. the adjacency information
of the position played
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 104

Understand Critical Wires
RWD : 8 bits
 The reward points calculated based on adjacencies
 In Unsigned Binary
P1PT : 8 bits
 Player 1 points
 In Hex
P2PT : 8 bits
 Player 2 points
 In Hex
PT : 8 bits
 The points of the current player
 In Hex
NPT : 8 bits
 New player points for the current player
 In Hex
Ptovf : 1 bit
The points overflow
 if it is 1, the new player points is above (255)10
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 105

Understand Critical Wires
P1add : 1 bit
 Player 1 adds when it is 1
P2add : 1 bit
 Player 2 adds when it is 1
Add : 1 bit
 The current player adds when it is 1
P1skip : 1 bit
 Player 1 skips when it is 1
P2skip : 1 bit
 Player 2 skips when it is 1
P1played : 1 bit
 Player 1 played when it is 1
P2played : 1 bit
 Player 2 played when it is 1
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 106

Understand Critical Wires
Clear : 1 bit
 Clear FFs, registers, counters, etc. during reset in Block 2 and Block 4 so
that it can play again
Clearp2ffs : 1 bit
 Clears Player 2 FFs, counters and registers
Shp1rds : 1 bit
Shows next two digits to Player 1 in state 1
Add : 1 bit
Shows that the current player has selected to add
Stp1pt : 1 bit
 Store Player 1 points
Stp2pt : 1 bit
 Store Player 2 points
Grd : 1 bit
 Signals to generate a new random digit
 The random digit counter output is stored as P2RD while P2RD and P1RD are
shifted to generate the new P1RD and RD
Bpds : 1 bit
Blink one or all displays slowly
Bpdf : 1 bit
Blocks a display fast after a display overflow
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 107

Understand Critical Wires
Clff : 1 bit
 Clears FFs in Block 2 so that the next player can play if
there is no overflow
S1 : 1 bit
 State 1 where when it is 1, the Ppm is in state 1
P2sturn : 1 bit
 Signals that Player 2 has the turn
 It is 1 when the Ppm is in state 4
Sysclk : 1 bit
 System clock of the operation diagram at 6 Hz to the digit
played
 P2clk : 1 bit
 The clock signal of Player 2 at 48 Hz
 Rdclk : 1 bit

The random digit counter clock at 192 Hz
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 108

Project Manager Actions and Reminders
 Make sure there is a CS2204 folder
 Make sure there is an experiment folder for
the current experiment

You can check the folder the current project is in
by selecting File -> Project Info
 Make sure the FPGA chip and its model are
correct when a new Xilinx project is created

You can check the FPGA chip and its model by
selecting File -> Project Type…
 The selections must be as follows
• The chip : Spartan
• The model : S10PC84
• Speed : 3
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 109

Project Manager Actions and Reminders
 If you copy a project completely and paste it as a
new project, its schematic files cannot be worked on
right away




After you open the schematics, they are all Non-Project
schematics
Close all the schematics
Close the schematics window
Open the schematics one by one on the Project Manager
window
 Double click on the schematic name on the upper left side for
each schematic file
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 110

Project Manager Actions and Reminders
 When you do the first Xilinx
IMPLEMENTATION or after clearing the
implementation data, you need to change
implementation options before clicking on
“Run” in the Implement Design Window

You can change the options by selecting Options…
in the same window and then
 Increase the Place & Route Level to the Highest Effort
on the “Options” window
 Click on the Edit Options… button for Implementation: in
the Program Options area of the “Options” window
 Click on Place and Route on the “Spartan Implementation
Options: Default” window
 Increase Router Options to 50 and 5 for both Routing
Passes and Delay-Based Cleanup Passes
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5
Page 111

Project Manager Actions and Reminders
 After a successful IMPLEMENTATION




The schematic files have a check mark next to them
The Design Entry button will have a check mark
The IMPLEMENTATION button has a check mark (after a
delay of minutes sometimes)
The PROGRAMMING button is highlighted
 If not, just click in anywhere in the Flow tab area of the
Project Manager window, it will be highlighted
 If the IMPLEMENTATION is not successful due to
errors, the IMPLEMENTATION button will have an
“X” mark

The error can be because of wrong chip selection or
schematic design errors
 Correct them then !
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 112

Project Manager Actions and Reminders
 After a Xilinx IMPLEMENTATION, read the
Implementation Log File for errors, warnings and
FPGA chip utilization

You can read the Implementation Log File by selecting
Reports -> Implementation Log File
 All No driver warnings must be corrected
• No Driver means, the wire is not connected to any
component output
 All Multiple drivers warnings must be corrected
• Multiple Drivers means, a wire is connected to multiple
component outputs
 Most No Load warnings can be ignored
• Because, the software warns that a component output is
not used, because you do not need the output
• But, if a component output is needed, and not connected,
then it is an error, the output must be connected to the
input of a component
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 113

Project Manager Actions and Reminders
 After performing several Xilinx IMPLEMENTATIONs, clear the
implementation data, by selecting Project -> Clear
Implementation Data

Back to back Xilinx IMPLEMENTATIONs use previous
implementation data that is unchanged to save time
 Over time, this implementation data becomes corrupt and the bit file
has errors
• Correct designs do not perform correctly on the FPGA board

Clearing the implementation data changes the implementation
options to the default ones





The schematic files will keep their check marks
The Design Entry button will keep its check mark
But, the IMPLEMENTATION button will have a question mark
The PROGRAMMING button will not be highlighted
The implementation options must be changed to the required ones again
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 114

Schematic Design Actions, Shortcuts &
Reminders
 Place team info on schematics

You can enter the team info by selecting File -> Table
Setup…
 Place your name & a partner name on Line1:
 Place names of the other two partners on Line 2:
 On Line3: place CS2204 – Section A/B/C/D/E/F – Spring 2007
 Press F2 to enter the Select & Drag Mode

Only, in this mode components can be deleted, rotated,
copied and pasted
 You can press ESC to enter the Select & Drag Mode
 Press F3 to get component library on screen



VCC is logic 1
GND is logic 0
To quickly locate a component, enter the first few letters of
the component in the bottom area of the SC Symbols window
 To locate XOR gates, just enter letter “X” and “O”
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 115

Schematic Design Actions, Shortcuts &
Reminders
 Press F4 to draw wires
 Press F5 to draw buses
 Press F7 to search for wires and components

To search for wires, select the Signal/Bus mode
 If the wire does not have a name, the software assigns one
that starts with a “$” symbol and ends with a “_” symbol
• Use the whole name to search for a wire

To search for a component, select the Instance mode
 If a component does not have a name, the software assigns one
that starts with “$I” symbols followed by a number
• Use the whole name to search for the component
 Press F8 to start simulation quickly
 Press F10 to refresh the screen
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 116

Schematic Design Actions, Shortcuts &
Reminders
 Press ctrl-c to copy a wire or a component selected


When components are copied, their labels are not copied !
You can copy from a schematic that belongs to another
project
 To open the schematic of another project, click on
button
in the upper left corner, then select the schematic file which
will be in another folder
 Press ctrl-v to paste a wire or a component
 Press ctrl-r/ctrl-l to rotate components right/left

Wires cannot be rotated !
 You can see how a Xilinx macro is designed (the
internal structure), do a Hierarchy Push, by selecting
Hierarchy -> Hierarchy Push
 You can close the macro internal design screen, by
selecting Hierarchy -> Hierarchy Pop
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 117

Schematic Design Actions, Shortcuts & Reminders
 Unless otherwise stated, use Xilinx macros instead of designing
them to save time
 Use buffers to rename wires
 Do not use unnecessary input/output buffers
 Do not use unnecessary input/output pads
 If you copy and paste components, their labels are not copied
and pasted by the software

You will need to “source” the schematic file to copy and paste
component labels as explained in the Advanced Xilinx and Digilent
Features handout
 Xilinx does not have high density ROM memory components

16x1-bit and 32x1-bit
 They may not be used at all
• If needed, its usage is described on page 9 of the Advanced
Xilinx and Digilent Features handout
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 118

Schematic Design Actions, Shortcuts &
Reminders
 Drawing buses by using Draw Buses button on the left
side :


Ppm buses are type None
Individual wires of a bus must have names the same as the
bus name
 The indices of individual wires start at 0 and are up to the
number of bus wires minus 1
• Bus NPT has 8 wires : NPT7, NPT6, NPT5,…, NPT1, NPT0

If a component generates a bus, there is no need to draw
the individual wires of the bus, unless a components needs
those individual wires
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 119

Schematic Design Actions, Shortcuts &
Reminders
 Beautify the schematic for documentation purposes

Place components of different sub/blocks separate from
each other to recognize them
 Write Comments, draw lines and rectangles and label
sub/blocks to identify them on the schematic for
documentation purposes
• Use the Graphics Toolbox button on the left :

Label components appropriately
 Wire names follow application and block partitioning naming
requirements
• Except for wires that are connected IBUFs, OBUFs, IPADs and
OPADs
 Component names start with a U
• Except if it is a BUF, IBUF, OBUF, IPAD or OPAD
 To label a component, right click on the component and select
Symbol Properties…
• Give the name in the Reference: section of the Symbol Properties
window
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 120

Schematic Design Actions, Shortcuts &
Reminders
 Beautify the schematic for documentation purposes


Do not leave components unused
Draw short wires and label them with the same name
 To label wires double click on the wire and enter the name in
the Net Name: area of the pop up window






Draw wires without unnecessary turn
Draw wires without tangling
Draw wires around components/labels/names
Do not short circuit input lines
Do not short circuit output lines
Do not have labels/attributes/components overlap
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 121

Schematic Design Actions, Shortcuts &
Reminders
 Perform integrity tests to catch simple
errors

You can do an integrity test of the current
schematic sheet, by selecting Options -> Integrity
Test for Current Sheet
 After the completion, a window may tell you to look at
the Project Manager window to read about warnings
detected, even if it says the test passed successfully
• Look at the Project Manager window, you will see warnings
in blue
• If the last line has the Schematic Contents OK line, there
is no need to correct anything
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 122

Schematic Design Actions, Shortcuts &
Reminders
 Perform logic simulations to catch logic errors

Press F8 to start simulation quickly
 You will see the SC Probes window
 To select the input wires to be simulated, click on the
Stimulator tool button of the SC Probes windows
 Then click on the input wires by precisely clicking on their
names to select them
• There will be a square gray box shown on the left side of the
input wire name
• Wires that have no name cannot be simulated, therefore, they
must be given names for simulation
• When selecting input bus wires, click on the bus wires in the
increasing index order : ABUS0, ABUS1, ABUS2,…
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 123

Schematic Design Actions, Shortcuts &
Reminders
 Perform logic simulations to catch logic errors

Press F8 to start simulation quickly
 You will see the SC Probes window :
 To select the output wires to be simulated, click on the Probe
tool button of the SC Probes windows :
 Then click on the output wires by precisely clicking on
their names to select them
• There will be a square gray box shown on the left side of
the output wire name
• Wires that have no name cannot be simulated, therefore,
they must be given names for simulation
• When selecting output bus wires, click on the bus wires in
the increasing index order : OBUS0, OBUS1, OBUS2,…
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 124

Schematic Design Actions, Shortcuts &
Reminders
 Perform logic simulations to catch logic errors

Press F8 to start simulation quickly
 You will see the SC Probes window :


To start the simulation, click on the Simulator button of the
SC Probes window :
Once you have the simulation window on the screen
 You will see the input wires listed and then the output wires on
the left side of the Logic Simulator window
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 125

Schematic Design Actions, Shortcuts &
Reminders
 Perform logic simulations to catch logic errors

Separate the input rows from the output rows by placing a
blank row between the input and output wires sets
 Click on the top output wire
 Make selections Signal -> Empty Rows -> Insert

Combine bus bits to reduce the number of rows
 Click on the top bus wire which has the lowest index (ABUS0)
 Press shift and simultaneously click on the highest order bus
wire (ABUS7) to select all the wires of the bus
• A turquoise rectangle covers the bus wires
 Right click on the turquoise rectangle and make the following
selections Bus -> Combine
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 126

Schematic Design Actions, Shortcuts &
Reminders
 Perform logic simulations to catch logic errors

In order to simulate the circuit, the input wires must be
first given new names
 Click on the Select Stimulators button :
• A keypad window will be shown
 Select an input wire by clicking on it (it will be covered by a
turquoise rectangle) and then click on any letter key on the
keypad, such as “q”
• To the right of the input wire, the new name “q” is shown
• To the right of “q”, the current value of the wire is shown
►
If it is a single wire, the value is Hi-Z
◊ This has to be changed to have correct simulations
► If it is a bus, the value is shown as capital letter “Z”
◊ This has to be changed as well for correct simulations
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 127

Schematic Design Actions, Shortcuts & Reminders
 Perform logic simulations to catch logic errors

To change the values of wires on the simulator window
 If it is a single wire, the value is Hi-Z :
• Just click on the Hi-Z line to make the value 0
►The value is shown to the right of name “q” as 0
• Click on the 0 value line again to make the value 1
►The value is shown to the right of name “q” as 1
 If it is a bus, the value is shown as capital letter “Z”
• Click on Logical States to give a value to the bus :
►The Stimulator State Selection window will be shown
• Click on the bus name, such as ABUS
• Enter an appropriate Hex value in the Bus State area, such as “FA”
► Appropriate means the Hex value must fit the width of the
bus : “FA” implies, the bus has at least eight wires
• Click on the Bus button of the Stimulator State Selection window :
►The value assigned is shown to the right of name “q” as “FA”
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 128

Schematic Design Actions, Shortcuts & Reminders
 Perform logic simulations to catch logic errors

To change the values of wires on the simulator window
 To have a clock signal as an input follow the steps below :
• Make sure the input signal is not renamed as “q”, “w” etc.
• Click on the input signal to select it
• Click on the Select Stimulators button :
• Click on Formula…
• Double click on C1: under Clocks
• Enter the following in the Edit Formula area :
• 100ns=H 100ns=L
► This means a periodic signal which is 100 ns 1 and 100 ns 0 is generated
► The periodic signal has a period of 200ns or a frequency of 5MHz
• Click Accept
• Click Close
• You will see the C1 button on the Select Stimulators window
highlighted
• Click on C1 so that the input signal is renamed C1
• Click on the Simulation Step button several times :
• You will see the periodic signal automatically generated and the
output values in response to that
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 129

Schematic Design Actions, Shortcuts &
Reminders
 Perform logic simulations to catch logic errors

Start simulating the circuit for different input combinations
 If the circuit has 4 or less inputs, then simulate the circuit for
all input combinations (test vectors)
• 16 or less number of input combinations (test vectors)
 If the circuit has more than 4 inputs, select a number of input
combinations (test vectors) then simulate the circuit for these
test vectors
• Which test vectors to choose is a very important task !


To simulate the circuit, click on the Simulation Step button
several times :
Observe the outputs
 If they are correct, try another input combination
 If wrong, return to the schematic and try to figure out why it
is wrong !
 If an output value is Hi-Z or Unknown, there is an error,
correct it
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 130

Schematic Design Actions, Shortcuts &
Reminders

Printing schematics
1) Double click on the Printer227 icon on your desktop and
wait about a minute to allow it to affect the printing
option
2) Zoom into an area of the schematic to print the area
3) Select File -> Print on the schematic window
4) Change the option to Current View Only on the Print
window
5) Click on Setup on the Print Window
6) Change the printer to HP Printer 8150 in Room 227
7) Click on Options to select Landscape printing if
necessary
8) Click OK as many times as needed to print the page
9) Print one copy of each area and then make copies of the
printed schematics for your partners
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 131


What to do if the testing on the board gives wrong
results even thought the design is correct ?
If the design is absolutely correct, here are the steps to
follow in sequence :
1)
2)
3)
4)
5)
6)
7)
8)
The FPGA board is turned on ?
SW9 is in the PROG position ?
The Bitronics Data Switch selects your PC ?
The FPGA type and model are correct ?
The implementation options are changed ?
There are not too many levels of folders to reach the project on
the PC ?
Clear the implementation data, close the software, restart the
software and do a new Xilinx IMPLEMENTATION

Does it work now ?

Delete the project, recreate the project, copy the schematic design
from the saved schematic file
Save the schematic file worked on in a separate folder

•
Does it work ?
•
Does it work ?
Download the zipped project from the course web site, unzip it, copy
the schematic design from the saved schematic file
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 132

What to do if the testing on the board gives
wrong results even thought the design is
correct ?
9) Repeat step 7, by using your partner’s working
schematic
10) Login to another PC and try steps 5 - 8
11) Ask from the TA to help you
a) The TA will login to your original PC and try steps 5 – 8
by using your schematic design and his/her S drive
b) The TA will login to another PC and try steps 5 – 8 by
using your schematic design and his/her S drive on the
new PC
c) The TA will inform the professor
12)If the project works on the second PC, inform
the lab supervisor, Mr. Keni Yip that the original
PC has a problem
CS 2204 Spring 2008 Lab 8 Experiment 4 - 5 Page 133