Transcript Lecture 1 - Introduction

EGRE 254 Digital Logic Design
Lecture 1
Dr. Jerry H. Tucker
1
Web page
• Class handouts, announcements, and other
information will be posted on the class web page
at http://www.people.vcu.edu/~jhtucker/s09egre254/index.html.
• Bookmark and monitor this page! There is a link
to it on my home page which you can find by
doing a Google search for Jerry Tucker.
2
Labs
• Everyone needs to be registered for Lab.
– Either the 2:00 or 4:00 sessions on Thursday.
– Due to the class size the lab will actually be divided
into three sections, however, you must be registered for
the original official time.
– Normally lab will be in room 237, but occasionally may
be in room 337.
– Monitor the class web page for changes in lab location
if there is no announcement go to room 237.
– Lab report guidelines are posted on the class web page.
– Not all labs will require a lab report.
– Most labs will be conducted with a partner.
– You should select a lab partner by next week.
3
Textbook
• We will use Digital Design Principles and Practices either
3rd or 4th editions by John Wakerly.
• The book may contain a CD with Xilinx software. This
software is obsolete. Don’t bother to install it. You may
want to go to
http://www.xilinx.com/support/download/in
dex.htm register and download and install the free
ISEWebPack and the ModelSim MXE simulator on your
home computer.
• You may also want to download and install the evaluation
version of Orcad form
http://www.cadence.com/downloads/orcad/request
form.aspx?dl=orcadDemo
• We will use this software in some labs.
4
Final course grades will be determined as follows:
Homework
10%
Laboratory
10%
Quizzes (2)
50%
Final exam
30%
Some curving may be used to determine the final letter grade
for this class. You may expect the grade dividing points to
be as follows:
Between A and B: 90-93.
Between B and C: 80-85.
Between C and D: 70-75.
Between D and F: 60-65.
The grade dividing points on the curve will be determined
primarily by gaps in the distribution of the final average. It
is not predetermined that a certain number of students will
receive a given grade.
5
Digital logic design (DLD)
• In this class take time to understand the
fundamental concepts and don’t get behind.
• If you do this, DLD will be an easy and interesting
course.
• Digital systems are simpler and better behaved
that analog systems. (Provided you follow the
rules.)
• This is because in digital systems we deal with
only two levels referred to as “0” and “1”.
– Sometimes the “0” level is referred to as “false” and the
“1” lever as true.
– In logic circuits voltages levels correspond to the “0”
and “1”. Typical “0” is a voltage near 0 volts, and “1” is
a higher voltage such as 5 volts.
6
Digital Circuits
• Digital Circuits are divided into two major
classifications.
• Combinational
U1A
1
3
2
U1B
74LS00
4
6
U2A
1
2
5
U1C
9
74LS00
8
– Consist of logic gates with no feedback.
– Output depends only on present input.
10
74LS06
74LS00
• Sequential
– Contain flip-flops or gates with feedback.
– Output depends on both present input and previous
inputs.
– Sequential circuits have memory.
U1A
1
3
2
U1B
74LS00
4
6
U2A
5
U1C
74LS00
1
2
9
8
2
3
D
CLK
Q
1
1
4
12
13
DFF
J
K
Q
Q
3
2
10
74LS06
74LS00
CLK
CLR
74LS107
7
U3A
U2A
1
2
6
1
3
2
4
5
74LS20
74LS00
We will typically use NAND gates and the 74LS logic
family. All other gates can be implemented using NAND
gates. 74LS gate outputs can drive about twenty 74LS
inputs. In practice you probably should not drive much
more that ten inputs.
8
2
1
0.0 V
9
10
Interfacing to non 74LS devices. Consider driving an LED.
V CC
D2
1
R2
R
IOH = -0.4 ma max
2
74 LS 04
IOL = 4.0 ma max for 74
LE D
Or
IOL = 8.0 ma max for 54
D1
1
2
74LS04
LED
R3
R
Dose it make any difference?
11
Operating region
12
13
Pin count as seen from the top. Notice notch!
14
Field Programmable Gate Arrays (FPGA’s) may contain the
equivalent of millions of gates in one IC.
15
16