Transcript EECS 252 Graduate Computer Architecture Lec 01

Appendix C: Pipelining
Original slides created by:
David Patterson
Electrical Engineering and Computer Sciences
University of California, Berkeley
http://www.eecs.berkeley.edu/~pattrsn
http://www-inst.eecs.berkeley.edu/~cs252
Outline:
MIPS – An ISA for Pipelining
5 stage pipelining
Structural Hazards
Data Hazards & Forwarding
Branch Hazards
Handling Exceptions
Floating Point Operations
A "Typical" RISC ISA
•
•
•
•
32-bit fixed format instruction (3 formats)
32 32-bit GPR (R0 contains zero, DP take pair)
3-address, reg-reg arithmetic instruction
Single address mode for load/store:
base + displacement
– no indirection
• Simple branch conditions
• Delayed branch
see: SPARC, MIPS, HP PA-Risc, DEC Alpha, IBM PowerPC,
CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3
r0
r1
°
°
°
r31
PC
lo
hi
0
Programmable storage
2^32 x bytes
31 x 32-bit GPRs (R0=0)
32 x 32-bit FP regs (paired DP)
HI, LO, PC
Arithmetic logical
Add, AddU, Sub, SubU, And, Or, Xor, Nor, SLT, SLTU,
AddI, AddIU, SLTI, SLTIU, AndI, OrI, XorI, LUI
SLL, SRL, SRA, SLLV, SRLV, SRAV
Memory Access
LB, LBU, LH, LHU, LW, LWL,LWR
SB, SH, SW, SWL, SWR
Control
32-bit instructions on word boundary
J, JAL, JR, JALR
BEq, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZAL,BGEZAL
Instruction format
Register-Register
31
26 25
Op
21 20
Rs1
16 15
Rs2
11 10
6 5
Rd
0
Opx
Register-Immediate
31
26 25
Op
21 20
Rs1
16 15
Rd
immediate
0
Branch
31
26 25
Op
Rs1
21 20
16 15
Rs2/Opx
immediate
0
Jump / Call
31
26 25
Op
target
0
Datapath vs Control
Datapath
Controller
signals
Control Points
•
•
Datapath: Storage, FU, interconnect sufficient to perform the desired
functions
–
–
Inputs are Control Points
Outputs are signals
Controller: State machine to orchestrate operation on the data path
–
Based on desired function and signals
5 Steps of MIPS Datapath
Instruction
Fetch
Instr. Decode
Reg. Fetch
Execute
Addr. Calc
Next SEQ PC
Adder
4
Zero?
RS1
PC <= PC + 4
Reg[IRrd] <= Reg[IRrs]
opIRop Reg[IRrt]
WB Data
L
M
D
MUX
Sign
Extend
Data
Memory
ALU
Imm
MUX MUX
IR <= mem[PC];
RD
Reg File
Inst
Memory
Address
RS2
Write
Back
MUX
Next PC
Memory
Access
Inst. Set Processor Controller
IR <= mem[PC];
PC <= PC + 4
JSR
A <= Reg[IRrs];
JR
br
if bop(A,b)
Ifetch
opFetch-DCD
ST
B <= Reg[IRrt]
jmp
RR
PC <= IRjaddr
r <= A opIRop B
RI
LD
r <= A opIRop IRim
r <= A + IRim
WB <= r
WB <= Mem[r]
PC <= PC+IRim
WB <= r
Reg[IRrd] <= WB
Reg[IRrd] <= WB
Reg[IRrd] <= WB
Outline:
MIPS – An ISA for Pipelining
5 stage pipelining
Structural Hazards
Data Hazards & Forwarding
Branch Hazards
Handling Exceptions
Floating Point Operations
5 Steps of MIPS Datapath
& Stage Registers
Execute
Addr. Calc
Instr. Decode
Reg. Fetch
Next SEQ PC
Next SEQ PC
Adder
4
Zero?
RS1
RD
RD
RD
MUX
Sign
Extend
MEM/WB
Reg[IRrd] <= WB
Data
Memory
WB <= rslt
EX/MEM
B <= Reg[IRrt]
rslt <= A opIRop B
ALU
A <= Reg[IRrs];
Imm
MUX MUX
PC <= PC + 4
ID/EX
IR <= mem[PC];
Reg File
IF/ID
Memory
Address
RS2
Write
Back
MUX
Next PC
Memory
Access
WB Data
Instruction
Fetch
Visualizing Pipelining
Time (clock cycles)
Reg
DMem
Ifetch
Reg
DMem
Reg
ALU
DMem
Reg
ALU
O
r
d
e
r
Ifetch
ALU
I
n
s
t
r.
ALU
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
Ifetch
Ifetch
Reg
Reg
Reg
DMem
Reg
Pipelining is not quite that easy!
• Limits to pipelining: Hazards prevent next
instruction from executing during its designated
clock cycle
– Structural hazards: HW cannot support this
combination of instructions (single person to fold and
put clothes away)
– Data hazards: Instruction depends on result of prior
instruction still in the pipeline (missing sock)
– Control hazards: Caused by delay between the fetching
of instructions and decisions about changes in control
flow (branches and jumps).
Outline:
MIPS – An ISA for Pipelining
5 stage pipelining
Structural Hazards
Data Hazards & Forwarding
Branch Hazards
Handling Exceptions
Floating Point Operations
One Memory Port/Structural Hazards
Figure A.4, Page A-14
Time (clock cycles)
Reg
DMem
Reg
DMem
Reg
DMem
Reg
ALU
Instr 4
Ifetch
ALU
Instr 3
DMem
ALU
O
r
d
e
r
Instr 2
Reg
ALU
I Load Ifetch
n
s
Instr 1
t
r.
ALU
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
Ifetch
Ifetch
Reg
Ifetch
Reg
Reg
Reg
DMem
Reg
One Memory Port/Structural Hazards
(Similar to Figure A.5, Page A-15)
Time (clock cycles)
Stall
DMem
Ifetch
Reg
DMem
Reg
ALU
Ifetch
Bubble
Instr 3
How do you “bubble” the pipe?
Reg
Reg
DMem
Bubble Bubble
Ifetch
Reg
Reg
Bubble
ALU
O
r
d
e
r
Instr 2
Reg
ALU
I Load Ifetch
n
s
Instr 1
t
r.
ALU
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
Bubble
DMem
Reg
Speed Up Equation for Pipelining
CPIpipelined  Ideal CPI  Average Stall cycles per Inst
Cycle Time unpipeline d
Ideal CPI  Pipeline depth
Speedup 

Ideal CPI  Pipeline stall CPI
Cycle Time pipelined
For simple RISC pipeline, CPI = 1:
Cycle Time unpipeline d
Pipeline depth
Speedup 

1  Pipeline stall CPI
Cycle Time pipelined
Example: Dual-port vs. Single-port
• Machine A: Dual ported memory (“Harvard
Architecture”)
• Machine B: Single ported memory, but its pipelined
implementation has a 1.05 times faster clock rate
• Ideal CPI = 1 for both
• Loads are 40% of instructions executed
SpeedUpA = Pipeline Depth/(1 + 0) x (clockunpipe/clockpipe)
= Pipeline Depth
SpeedUpB = Pipeline Depth/(1 + 0.4 x 1) x (clockunpipe/(clockunpipe / 1.05)
= (Pipeline Depth/1.4) x 1.05
= 0.75 x Pipeline Depth
SpeedUpA / SpeedUpB = Pipeline Depth/(0.75 x Pipeline Depth) = 1.33
• Machine A is 1.33 times faster
Outline:
MIPS – An ISA for Pipelining
5 stage pipelining
Structural Hazards
Data Hazards & Forwarding
Branch Hazards
Handling Exceptions
Floating Point Operations
Data Hazard on R1
Figure A.6, Page A-17
Time (clock cycles)
and r6,r1,r7
or
r8,r1,r9
xor r10,r1,r11
Ifetch
DMem
Reg
DMem
Ifetch
Reg
DMem
Ifetch
Reg
DMem
Ifetch
Reg
ALU
sub r4,r1,r3
Reg
ALU
Ifetch
ALU
O
r
d
e
r
add r1,r2,r3
WB
ALU
I
n
s
t
r.
MEM
ALU
IF ID/RF EX
Reg
Reg
Reg
Reg
DMem
Reg
Three Generic Data Hazards
• Read After Write (RAW)
InstrJ tries to read operand before InstrI writes it
I: add r1,r2,r3
J: sub r4,r1,r3
• Caused by a “Dependence” (in compiler nomenclature).
This hazard results from an actual need for
communication.
Three Generic Data Hazards
• Write After Read (WAR)
InstrJ writes operand before InstrI reads it
I: sub r4,r1,r3
J: add r1,r2,r3
K: mul r6,r1,r7
• Called an “anti-dependence” by compiler writers.
This results from reuse of the name “r1”.
• Can’t happen in MIPS 5 stage pipeline because:
– All instructions take 5 stages, and
– Reads are always in stage 2, and
– Writes are always in stage 5
Three Generic Data Hazards
• Write After Write (WAW)
InstrJ writes operand before InstrI writes it.
I: sub r1,r4,r3
J: add r1,r2,r3
K: mul r6,r1,r7
• Called an “output dependence” by compiler writers
This also results from the reuse of name “r1”.
• Can’t happen in MIPS 5 stage pipeline because:
– All instructions take 5 stages, and
– Writes are always in stage 5
• Will see WAR and WAW in more complicated pipes
Forwarding to Avoid Data Hazard
Figure A.7, Page A-19
or
r8,r1,r9
xor r10,r1,r11
Reg
DMem
Ifetch
Reg
DMem
Ifetch
Reg
DMem
Ifetch
Reg
ALU
and r6,r1,r7
Ifetch
DMem
ALU
sub r4,r1,r3
Reg
ALU
O
r
d
e
r
add r1,r2,r3 Ifetch
ALU
I
n
s
t
r.
ALU
Time (clock cycles)
Reg
Reg
Reg
Reg
DMem
Reg
HW Change for Forwarding
Figure A.23, Page A-37
NextPC
mux
What circuit detects and resolves this hazard?
mux
Immediate
MEM/WR
EX/MEM
ALU
mux
ID/EX
Registers
Data
Memory
Forwarding to Avoid LW-SW Data Hazard
Figure A.8, Page A-20
or
r8,r6,r9
xor r10,r9,r11
Reg
DMem
Ifetch
Reg
DMem
Ifetch
Reg
DMem
Ifetch
Reg
ALU
sw r4,12(r1)
Ifetch
DMem
ALU
lw r4, 0(r1)
Reg
ALU
O
r
d
e
r
add r1,r2,r3 Ifetch
ALU
I
n
s
t
r.
ALU
Time (clock cycles)
Reg
Reg
Reg
Reg
DMem
Reg
Data Hazard Even with Forwarding
Figure A.9, Page A-21
and r6,r1,r7
or
r8,r1,r9
DMem
Ifetch
Reg
DMem
Reg
Ifetch
Ifetch
Reg
Reg
Reg
DMem
ALU
O
r
d
e
r
sub r4,r1,r6
Reg
ALU
lw r1, 0(r2) Ifetch
ALU
I
n
s
t
r.
ALU
Time (clock cycles)
Reg
DMem
Reg
Data Hazard Even with Forwarding
(Similar to Figure A.10, Page A-21)
Reg
DMem
Ifetch
Reg
Bubble
Ifetch
Bubble
Reg
Bubble
Ifetch
and r6,r1,r7
or r8,r1,r9
How is this detected?
Reg
DMem
Reg
Reg
DMem
ALU
sub r4,r1,r6
Ifetch
ALU
O
r
d
e
r
lw r1, 0(r2)
ALU
I
n
s
t
r.
ALU
Time (clock cycles)
Reg
DMem
Software Scheduling to Avoid Load Hazards
Try producing fast code for
a = b + c;
d = e – f;
assuming a, b, c, d ,e, and f in memory.
Slow code:
LW
Rb,b
LW
Rc,c
ADD
Ra,Rb,Rc
SW
a,Ra
LW
Re,e
LW
Rf,f
SUB
Rd,Re,Rf
SW
d,Rd
Fast code:
LW
LW
LW
ADD
LW
SW
SUB
SW
Rb,b
Rc,c
Re,e
Ra,Rb,Rc
Rf,f
a,Ra
Rd,Re,Rf
d,Rd
Compiler optimizes for performance. Hardware checks for safety.
Outline:
MIPS – An ISA for Pipelining
5 stage pipelining
Structural Hazards
Data Hazards & Forwarding
Branch Hazards
Handling Exceptions
Floating Point Operations
22: add r8,r1,r9
Reg
DMem
Ifetch
Reg
DMem
Ifetch
Reg
DMem
Ifetch
Reg
ALU
r6,r1,r7
Ifetch
DMem
ALU
18: or
Reg
ALU
14: and r2,r3,r5
Ifetch
ALU
10: beq r1,r3,36
ALU
Control Hazard on Branches
Three Stage Stall
36: xor r10,r1,r11
What do you do with the 3 instructions in between?
How do you do it?
Where is the “commit”?
Reg
Reg
Reg
Reg
DMem
Reg
Branch Stall Impact
• If CPI = 1, 30% branch,
Stall 3 cycles => new CPI = 1.9!
• Two part solution:
– Determine branch taken or not sooner, AND
– Compute taken branch address earlier
• MIPS branch tests if register = 0 or  0
• MIPS Solution:
– Move Zero test to ID/RF stage
– Adder to calculate new PC in ID/RF stage
– 1 clock cycle penalty for branch versus 3
Pipelined MIPS Datapath
Instruction
Fetch
Figure A.24, page A-38
Execute
Instr. Decode
Addr. Calc
Reg. Fetch
Adder
Adder
Zero?
RS1
RD
RD
• Interplay of instruction set design and cycle time.
RD
MUX
Sign
Extend
MEM/WB
Data
Memory
EX/MEM
ALU
MUX
ID/EX
Imm
Reg File
IF/ID
Memory
Address
RS2
WB Data
4
Write
Back
MUX
Next
SEQ PC
Next PC
Memory
Access
Four Branch Hazard Alternatives
#1: Stall until branch direction is clear
#2: Predict Branch Not Taken
–
–
–
–
–
Execute successor instructions in sequence
“Squash” instructions in pipeline if branch actually taken
Advantage of late pipeline state update
47% MIPS branches not taken on average
PC+4 already calculated, so use it to get next instruction
#3: Predict Branch Taken
– 53% MIPS branches taken on average
– But haven’t calculated branch target address in MIPS
• MIPS still incurs 1 cycle branch penalty
• Other machines: branch target known before outcome
Four Branch Hazard Alternatives
#4: Delayed Branch
– Define branch to take place AFTER a following
instruction
branch instruction
sequential successor1
sequential successor2
........
sequential successorn
branch target if taken
Branch delay of length n
– 1 slot delay allows proper decision and branch target
address in 5 stage pipeline
– MIPS uses this
Scheduling Branch Delay Slots
A. From before branch
add $1,$2,$3
if $2=0 then
delay slot
becomes
B. From branch target
sub $4,$5,$6
add $1,$2,$3
if $1=0 then
delay slot
becomes
if $2=0 then
add $1,$2,$3
add $1,$2,$3
if $1=0 then
sub $4,$5,$6
C. From fall through
add $1,$2,$3
if $1=0 then
delay slot
or $7,$8,$9
sub $4,$5,$6
becomes
add $1,$2,$3
if $1=0 then
or $7,$8,$9
sub $4,$5,$6
• A is the best choice, fills delay slot & reduces instruction count (IC)
• In B, the sub instruction may need to be copied, increasing IC
• In B and C, must be okay to execute sub when branch fails
Delayed Branch
• Compiler effectiveness for single branch delay slot:
– Fills about 60% of branch delay slots
– About 80% of instructions executed in branch delay slots useful in
computation
– About 50% (60% x 80%) of slots usefully filled
• Delayed Branch downside: As processor go to deeper pipelines
and multiple issue, the branch delay grows and need more than
one delay slot
– Delayed branching has lost popularity compared to more expensive
but more flexible dynamic approaches
– Growth in available transistors has made dynamic approaches
relatively cheaper
Evaluating Branch Alternatives
Pipeline speedup =
Pipeline depth
1 +Branch frequency Branch penalty
Assume 4% unconditional branch, 6% conditional branch- untaken, 10%
conditional branch-taken
Scheduling
Branch
CPI
speedup v.
speedup v.
scheme
penalty
unpipelined
stall
Stall pipeline
3 1.60
3.1
1.0
Predict taken
1 1.20
4.2
1.33
Predict not taken
1 1.14
4.4
1.40
Delayed branch
0.5 1.10
4.5
1.45
Outline:
MIPS – An ISA for Pipelining
5 stage pipelining
Structural Hazards
Data Hazards & Forwarding
Branch Hazards
Handling Exceptions
Floating Point Operations
• Exception: An unusual event happens to an instruction during
its execution
– Examples: divide by zero, undefined opcode
• Interrupt: Hardware signal to switch the processor to a new
instruction stream
– Example: a sound card interrupts when it needs more
audio output samples (an audio “click” happens if it is left
waiting)
• Problem: It must appear that the exception or interrupt must
appear between 2 instructions (Ii and Ii+1)
– The effect of all instructions up to and including Ii is
totalling complete
– No effect of any instruction after Ii can take place
• The interrupt (exception) handler either aborts program or
restarts at instruction Ii+1
Precise Exceptions in Static Pipelines
Key observation: architected state only
change in memory and register write stages.
Outline:
MIPS – An ISA for Pipelining
5 stage pipelining
Structural Hazards
Data Hazards & Forwarding
Branch Hazards
Handling Exceptions
Floating Point Operations
WAR and WAW hazards may appear because instructions have different lengths