Transcript TRAMS - Euretile

Carbon Nanotube Technology
An Alternative in Future SRAM memories
UPC
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Introduction
• In Si-bulk CMOS technology the variability of the device parameters is a key
drawback and it may be a limiting factor for further miniaturizing nodes.
• OBJECTIVE: to evaluate the variability in Carbon nanotube Field Effect
Transistor (CNFET) as well as its real capability to be a promising alternative
to Si-CMOS technology.
1. Impact of carbon nanotube (CNT) diameter variations and the presence of
metallic CNTs in the transistor (device level).
2. Comparison between Si-CMOS and CNFET 6T SRAM cells (circuit level).
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Device level
Carbon Nanotubes (CNTs)
Carbon
nanotube
Chiral vector
angle of the atom
arrangement along
the tube
Ch = na1 + ma2 º (n,m)
Graphene
Diameter
DCNT =
3a0
p
Behaviour
n 2 + m 2 + nm
a0 = 0.142nm
Rest of [(n - m) /3] = 0
Rest of [(n - m) /3] ¹ 0
Metallic
Semiconducting
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Device level
Carbon Nanotube Field Effect Transistors (CNFETs)
An “Ideal” MOSFET-like CNFET is formed by 1 or more semiconducting
CNTs perfectly aligned and well-positioned whose section under the gate is
intrinsic and the s/d extension regions are n/p doped.
Promising candidates to replace silicon CMOS due to its high performance
There are some imperfections inherent to CNT
synthesis and CNFET manufacturing process that
may eclipse the expectations
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Device level
SOURCES OF VARIATION
CNT growth process
CNFET manufacturing process
NO control of chirality
• Percentage of m-CNTs
• Diameter variations
• S/D doping variations
• Mispositioned and misaligned CNTs
Semiconducting CNTs
Metallic CNTs
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Device level
CNFET device model [1]
Fixed parameters
Variable parameters
Power supply
0.9V
Oxide thickness
4nm
Gate/Source/Drain length (CNT)
16nm
Width of the metal gate
36nm
CNT pitch
4nm
Number of CNTS per device (N)
Nominal:8
Range:4-12
CNT diameter (D)
1-6 nm
Chi distribution
Metallic CNT proportion (TM )
0% - 33%
[1] J. Deng and H.-S. Wong, “A compact spice model for carbon-nanotube field-effect transistors including nonidealities
and its application part II: Full device model and circuit performance benchmarking,” Electron Devices, IEEE
Transactions on, vol. 54, no. 12, pp. 3195–3205, 2007.
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Device level
Monte Carlo experiment
Example of IDS − VDS distribution for 50 CNFET samples.
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Device level
STD (σ) of VTH and K
Percentage of variation (100x3σ/μ)
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Circuit level
Variability analysis and performance in CMOS and CNFET SRAM 6T cells
PTM
Technology 32nm 22nm
T
VDD
16nm 11nm
1V
1V
TRAMS WP1
CNFET
16nm 18nm
13nm
8nm
9nm
6.5nm W=32nm, L=16nm
1V
0.7V
0.7V
8 tubes
1V
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Circuit level
CNFET SRAM cell versus Si-MOSFET SRAM cell (nominal comparison)
160
139.8
140
120
105
95.76
100
87.01
80
Write me (ps)
73.15
57.42
60
Access me (ps)
40
22.28
20
19.44
16.73
23.42
20.97
7.77
0
32nm
22nm
16nm
PTM
32nm
Static Power (pW)
109.60
Dynamic power (mW) 7.17
Read SNM (mV)
296
2
0.29
Cell area (mm )
18nm
22nm
112.40
4.91
262.90
0.14
13nm
16nm
279.60
3.94
218
0.09
CNFET
TRAMS WP1
18nm
13nm
6
11.39x10 8.11x106
1.53
1.26
202.80
195.50
0.07
0.045
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
CNFET
8 tubes
5.82
3.06
302.50
0.09
Circuit level
CNFET SRAM cell versus Si-MOSFET SRAM cell (variability comparison)
CNFET
Technology
NCNFET
VTH
m (V)
0.12
PCNFET
VTH
s(V)
0.0187
m(V)
-0.12
Random 6T cell
100 x 1 s/average
VTH
s(V)
0.0187
15.58%
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Circuit level
CNFET SRAM cell versus Si-MOSFET SRAM cell (variability comparison)
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Circuit level
CNFET SRAM cell versus Si-MOSFET SRAM cell (variability comparison)
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Device level
Conclusions
• CNFETs are promising candidates to replace Si-MOSFETs due to their high
current driving capability, tolerance to temperature and low leakage currents.
• Manufacturing variability, that is one of the key limiting factors in silicon-MOS
technology, has been investigated for such CNFET devices.
• Considering a range of metallic tubes from 33% (current growth methods) to 0%
(perfection) and a realistic distribution of diameters, it has been shown that the
variability of both K factor and VTH is lower than CMOS for transistors with just 8
nanotubes, and much better for 12 tubes.
• In a future scenario with a narrower distribution of CNT diameters, variation for
both parameters could reach levels from 15% to 25%, fact that would allow a
design procedure without the stress caused by variability in current conventional
technology.
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Circuit level
Conclusions
• CNFETs can be also considered as a potential alternative to CMOS in memory
systems.
• CNT technology presents better performance than CMOS technologies.
However the implementation maturity of CNFET is still pending of several years
of development.
• Variability analysis shows as a promising prospect, that even for todays
CNFETs performance, its variability is comparable with that of Si-MOS
technology in a scenario which we have called ”moderated”.
• Therefore, improvements in the control of chirality, the variability of CNFETs
could be lower than in that moderated scenario.
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Thanks for your attention!
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Device level
Carbon Nanotubes (CNTs)
Carbon
nanotube
Diameter & VTH
DCNT =
Eg
Graphene
3a0
p
n 2 + m 2 + nm
3 aVp
Vth »
=
2q
3 eDCNT
a0 = 0.142nm
a » 2.49 A˙
Vp » 3.033eV
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Device level
Mean (μ) of VTH and K
• Mean of Vth
as Tm
• Mean of K
as Tm
• Mean of Vth
as N
• Mean of K
as N
Eg
3 aVp
Vth »
=
2q
3 eDCNT
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011