Transcript PPT slides - Electrical and Computer Engineering

Jennifer Winikus
Computer Engineering Seminar
Michigan Technological University
February 10,2011
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Presentation based on :
Gregory Chen, Dennis Sylvester, David Blaauw, and Trevor Mudge
IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 18
No. 11, November 2010
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SRAM Performance Background
SRAM 6T and 8T designs
Experiment Methodology
Experimental Results
Conclusions
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Reduction in energy consumption is a high
priority objective for electronics
RAM cells are optimized by utilizing
transistors instead of flip flops to improve
density
Transistors have increase in “failure” as VDD is
minimized near and below VTH
Simulations of 8T and 6T SRAM at various
sizes, VDD, VTH performed to analyze for
future applications
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RAM is the acronym for Random Access
Memory
 Utilized by computers and digital
devices as a temporary memory storage
to store data as it is processed
 RAM and Processor speeds are the main
components in the speed of a computer
except for saving functions that the
hard drive capabilities factor in
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Acronym for Static Random Access Memory
Denser then flip flops
Faster then DRAM
Holds the data as long as power is applied
Form arrays on the RAM chips
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Three power regions
exist for Transistors:
triode, saturation and
cut-off
Near Threshold region
is classified as between
400 and 700 mV
Power Regions in MOSFET
http://en.wikipedia.org/wiki/File:IvsV_mosfet.png
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The shifting of VTH for each
transistor independently
Reduces Static Noise Margin
Causes mismatches within
cells
More predominate influence
on system at smaller VDD
Robustness is reduced with
Random Dopant Fluctuation
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Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design."
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI)
SYSTEMS 18.11 (2010): 1590-1598.
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Researchers at MIT have
established that in general
the relationship between
total energy, energy leakage
and Voltage in terms of the
energy per ALU cycle
ALU cycles are computer
architecture’s actions
 ALU’s include read and
write
Advances in Ultra-Low-Voltage Design
Joyce Kwong, Anantha P. Chandrakasan,
Massachusetts Institute of Technology
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Designs are based around desired read and
write speeds and stability
Cross coupled invertors are responsible for
holding the state
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The voltage threshold in the MOSFET in
which below the threshold the transistor is
essentially off, only leakage current passes
between the drain and source
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Read is performed by prechargin the cell and
floating the bitline
Write is performed by driving opposite values
to the bitline overriding the wordline
Chen, Gregory, et al. "Yield-Driven Near-Threshold
SRAM Design." IEEE TRANSACTIONS ON VERY
LARGE SCALE INTEGRATION (VLSI) SYSTEMS
18.11 (2010): 1590-1598.
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Read Upset
 The voltage applied to the node holding the zero
value is flipped due to noise
 Dependent on the pass gate strength
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Write
Timing
Hold
 Static Noise Margin over powers the cross-
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coupled invertors causing the state being stored
to flip
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Useful for independent
read-write ports, done by
having adding two
additional stacked
negative channel FETS to
the 6 cell to isolate the
read and write ports from
each other
2/10/2011
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Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM
Design." IEEE TRANSACTIONS ON VERY LARGE SCALE
INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598.
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The addition of a separate Read Bitline
eliminates the read failure that occurs in the
6T cell
Benefit of having the separate ports is that
the remaining 6 transistors can be sized and
doped to get the desired write stability
Failure mechanisms are otherwise the same
as the 6T
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An alternative to sizing modification
The premise is the modification of voltage
thresholds for behaviors such that failures are
prevented
 In a duel port structure the word line voltage can be
reduced when read process is performed
 The implementation is done through addition of
diodes
 More complex drivers and decoding is needed with
this methodology
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Modification of the threshold voltage of the
transistors for the design specific goals
In application the tuning of MOSFETs are
done by exciting dopants in the drain and
source with laser pulses to achieve desired
threshold voltages
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8T SRAM is typically 33% larger then a 6T cell
VTH is optimized separately for the SRAM and
the Logic to improve robustness and
performance
Sizing alterations can be minimized by
utilizing Assist Circuits
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The experiment
methodology is an
incremental conditioning
structure
Only Word Line Drivers, Bit
Line Drivers and bit cells are
considered
Chen, Gregory, et al. "Yield-Driven NearThreshold SRAM Design." IEEE
TRANSACTIONS ON VERY LARGE SCALE
INTEGRATION (VLSI) SYSTEMS 18.11 (2010):
1590-1598.
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Monte Carlo
 To account for high yeild systems like 8-kb SRAM with a 99% yeild, the
failure rate is on the order of 10-7, which requires atleast 10 million
simulations
 SRAM with caches larger then 8-kb have smaller failure rates in which
more simulations would be needed
Definition: Monte Carlo is the art of approximating an expectation by the
sample mean of a function of simulated random variables(UC Berkley)
Importance Sampling
 A unique probability density function is chosen for each transistor
 Choosing a relative range to choose the samples from
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Based on the percent
error seen over many
iterations, using the
importance sampling
20,000 samples is
sufficient for accurate
results
 Monte Carlo sampling
would require 1012
samples for accurate
results
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Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE
TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11
(2010): 1590-1598.
21
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The selected threshold
voltages are chosen by
choosing random values from
within the sample probability
distribution in which the
normal distribution is shifted
to induce a higher probability
of failure
Selectively choosing the
region speeds up analysis by
eliminating samples from
regions that are not of
Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE
TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11
interest of the experiment (2010): 1590-1598.
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Measured using Static Noise Margin or
Corner Cases
Determines if optimization is complete
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Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE
TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11
(2010): 1590-1598.
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Activity Factor is the average fraction of bit
cells accessed per cycle
Vmin is the voltage in which the energy
needed per operation is minimized
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Robustness is
controlled to be
constant through
the modification of
the size of the Bit
Cells.
This allows for VTH
tuning
Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design."
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI)
SYSTEMS 18.11 (2010): 1590-1598.
2/10/2011
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L1- small in size, high in activity, total energy
is mostly dynamic
L2- larger in size then L1, lower activity
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The energy reduction capability by tuning is most significantly seen in the 8T, a
61% reduction, including sizing as well results in an 83% energy reduction for the
8T cell
Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE
TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11
(2010): 1590-1598.
2/10/2011
J Winikus EE5900
Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM
Design." IEEE TRANSACTIONS ON VERY LARGE SCALE
INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598.
28
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The activity behavior
of the circuit is a
substantial
controlling factor in
Vmin and Emin
Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS
ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598.
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The relationship
produced between
activity factor and Vmin
demonstrates that the
less activity the higher
the Vmin
Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE
TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11
(2010): 1590-1598.
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Of the components
that assist circuit has
been applied the only
is beneficial in the
sub threshold region
for the overdriven
word line
Chen, Gregory, et al. "Yield-Driven Near-Threshold
SRAM Design." IEEE TRANSACTIONS ON VERY
LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11
(2010): 1590-1598.
2/10/2011
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Performance is
compromised with
voltage reduction, but
is minimized with the
use of assists
Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM
Design." IEEE TRANSACTIONS ON VERY LARGE SCALE
INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598.
2/10/2011
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The parabolic response of the
energy cost per bit access for the
write line displays the
correspondence with the Vmin as
below the approximate value the
energy increases again
Below about 650 mV assist
drooping is no longer considered
to assist the circuit
Leakage increases in a near
exponential behavior below Vmin
Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design."
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI)
SYSTEMS 18.11 (2010): 1590-1598.
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Assist circuit design
benefits in this result
for minimum voltage
capabilities
Energy cost increases
with activity
Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE
INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598.
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With low failure rates, Importance Sampling
is more efficient then Monte Carlo Sampling
Scaling to 300mV for 8T cells achieves 83%
energy reduction
In effort to reduce power and maintain
function-ability size is the compromise or
through the addition of assist circuit
Assist modification of certain functional
components is beneficial in failure prevention
as voltage decreases
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In the computer based 21st Century there is
the drive for faster computing, smaller
devices and less power consumption
The results display that at this point tuning
threshold voltages is the most promising
advancement to forward the consumer
desires
The results express the trade off that exists,
size or power, speed or power
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Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE
TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI)
SYSTEMS 18.11 (2010): 1590-1598.
R.P. Lu, A.D. Ramirez, B.W. Offord, and S.D. Russell of SPAWAR Systems
Center Pacific for the Office of Naval Research.“Threshold Voltage Tuning
of Metal-Gate MOSFETs Using an Excimer Laser”.
http://www.techbriefs.com/component/content/article/8013
Advances in Ultra-Low-Voltage Design .Joyce Kwong, Anantha P.
Chandrakasan, Massachusetts Institute of Technology.
http://www.ieee.org/portal/site/sscs/menuitem.f07ee9e3b2a01d06bb930
5765bac26c8/index.jsp?&pName=sscs_level1_article&path=sscs/08Fall&f
ile=Kwong.xml&xsl=article.xsl
Eric C. Anderson, 1999, UC Berkeley. “Lecture Notes for Stat 578C”
http://ib.berkeley.edu/labs/slatkin/eriq/classes/guest_lect/mc_lecture_no
tes.pdf
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