Transcript Hsin-I Liu

On-Chip ECC for Low-Power
SRAM Design
Hsin-I Liu
EE 241 Project
5/9/2005
Outline
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Introduction to low-power SRAM
Introduction on error correction code
Analysis of data retention voltage in
SRAM
Simulations and results
5/9/2005
EE 241 Project
Low-Power SRAM
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Concept: Reduce the standby Vdd to data retention
voltage (DRV)
VTC of SRAM cell inverters
0.4
VDD=0.4V
2
V (V)
0.3
0.2 V =0.18V
DD
0.1
VTC1
VTC2
0
0
0.1
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0.2
V1 (V)
0.3
0.4
EE 241 Project
250
350
SRAM column
200
300
150
250
100
200
50
150
0
0
100
40
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80
SRAM row
120
Histogram of 32K SRAM cells
Modeling DRV
6000
5000
4000
3000
2000
SRAM
Chip DRV
1000
0
100
200
300
400
DRV (mV)
DRV is modeled as i.i.d.
gamma random variable
DRV  60mV+10mVG (5,1)
1
i
g (5,1) (x )    x  e  x
i 0 i !
i
EE 241 Project
5
i
Error Correction Code
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Adding parity check into information
Non-trivial binary code
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Easy to encode
Parameters fixed
Hamming code, Golay code
n symbols
Linear block code
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Parameters flexible
Reed-Solomon code
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Least parity overhead
EE 241 Project
k information
symbols
n-k parity
symbols
Applying ECC to SRAM
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Latency
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In proportional to block size
In this project: Hamming (15,11),
Golay(23,12), and RS(15,11)
Implementation characteristics are wellknown
EE 241 Project
Model Setup
r redundant rows
Memory size: M× N
ECC block size: n
info length: i
Standby cycles: T
M rows
Row redundancy: r rows
ECC
Metrics:
n M r
codec
Eb  (
Vdds tan dby 2 
Vddactive 2 ) / DRV02
i M
iT
Ob 
i info
n symbols
codec
i
5/9/2005
ECC
EE 241 Project
ECC
N columns
ECC
r redundant rows
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M rows
Model Analysis
ECC
ECC
i info
n symbols
N columns
ECC
ECC
For certain standby voltage, retention
ability can be modeled as Bernoulli r.v.
For certain pe of a row, pe of a block
can be derived
Inside a block, pe of each cell can be
found by solving binomial distribution
Row redundancy can also be modeled
as binomial r.v.
5/9/2005
EE 241 Project
Results
225
250
215
Standby Voltage
Standby Voltage (mV)
220
200
150
100
Pe=2%
205
Pe=5%
Pe=8%
200
Hamming
50
Pe=1%
210
Pe=10%
RS
195
Pe=15%
Golay
0
190
0
200
400
600
800
1000
1200
0
200
# of cells in a row
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400
600
800
1000
# of cells in a row
EE 241 Project
1200
1400
1600
Results (cont.)
30%
Memory overhead
25%
20%
15%
256
10%
512
1024
5%
0%
0%
2%
4%
6%
8%
10%
12%
14%
16%
Pe in a row
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EE 241 Project
Results (cont.)
Number
of columns
Standby Voltage (mV)
Hamming
Golay
256
201.36
194.78
176.36
512
206.53
198.59
179.26
1024
210.04
201.76
182.12
9.091
22.727
58.333
Hardware
overhead
(gates/bit)
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RS
EE 241 Project
Conclusion
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Hamming code introduces the least
overhead
For short waiting time, Hamming code
can reduce Eb from 50% to 2x
As waiting time goes to infinity, ReedSolomon saves the power by 3x
5/9/2005
EE 241 Project