Transcript IC design styles

Packaging, testing and (good design practices)
Jorgen Christiansen
Packaging, Testing and good design practices
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Package types
Cooling
I/O signals
How to test IC’s
What not to do: design practices (if time allows)
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Requirements to package
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Protect circuit from external environment
Protect circuit during production of PCB
Mechanical interface to PCB
Interface for production testing
Good signal transfer between chip and PCB
Good power supply to IC
Cooling
Small
Cheap
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Materials
• Ceramic
– Good heat conductivity
– Hermetic
– Expensive ( often more expensive than chip itself !)
• Metal (has been used internally in IBM)
– Good heat conductivity
– Hermetic
– Electrical conductive (must be mixed with other material)
• Plastic
– Cheap
– Poor heat conductivity
Can be improved by incorporating metallic heat plate.
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Cooling
• Package must transport heat from IC to
environment
• Heat removed from package by:
– Air:
– PCB:
– Liquid:
Natural air flow, Forced air flow
improved by mounting heat sink
Transported to PCB by package pins
Used in large mainframe computers
Resistive equivalent
Heat sink
IC dice
Package
I = heat power
V= temperature
R = K/watt
PCB
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• Package types:
– Below 1 watt:
– Below 5 watt:
– Up to 30 watt:
Passive heat sink
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Plastic
Standard ceramic
Special
Active heat sink
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60 layers MCM substrate
Water cooled mainframe computer
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Chip mounting
• Pin through hole
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Pins traversing PCB
Easy manual mounting
Problem passing signals between pins on PCB (All layers)
Limited density
• Surface Mount Devices (SMD)
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Small footprint on surface of PCB
Special machines required for mounting
No blocking of wires on lower PCB layers
High density
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Traditional packages
• DIL (Dual In Line)
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Package inductance:
1 - 20 nH
Low pin count
Large
• PGA (Pin Grid Array)
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High pin count (up to 400)
Previously used for most CPU’s
• PLCC (Plastic leaded chip carrier
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Limited pin count (max 84)
Large
Cheap
SMD
• QFP (Quarter Flat pack)
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High pin count (up to 300)
small
Cheap
SMD
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Modern package types
• BGA (Ball Grid Array)
• Small solder balls to connect to
board
• small
• High pin count
• Cheap
• Low inductance
Package inductance:
1 - 5 nH
• CSP (Chip scale Packaging)
• Similar to BGA
• Very small packages
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• MCP (Multi Chip Package)
– Mixing of several technologies in same component
– Yield improvement by making two chips instead of one
P6: processor + second level cache
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Chip to package connection
• Wire bonding
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Only periphery of chip available for IO connections
Mechanical bonding of one pin at a time (sequential)
Cooling from back of chip
High inductance (~1nH)
• Flip-chip
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Whole chip area available for IO connections
Automatic alignment
One step process (parallel)
Cooling via balls (front) and back if required
Thermal matching between chip and substrate required
Low inductance (~0.1nH)
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Multiple Chip Module (MCM)
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Increase integration level of system (smaller size)
Decrease loading of external signals > higher performance
No packaging of individual chips
Problems with known good die:
– Single chip fault coverage: 95%
– MCM yield with 10 chips: (0.95)10 = 60%
• Problems with cooling
• Expensive (OK for military)
• No commercial success
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Complete PC in MCM
• Now they put all this into a single chip (SOC)
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Chip stacking
• Gluing bare chips on top of
each other within a
package
– Where it makes sense to put
many chips of same kind in
very small volume
– Each chip must have limited
power dissipation.
– Limited pin count per chip or
common bus
– Memories: DRAM, FLASH
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Signal Interface
• Transfer of IC signals to PCB
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Package inductance.
PCB wire capacitance.
L - C resonator circuit generating oscillations.
Transmission line effects may generate reflections
Cross-talk via mutual inductance
L-C Oscillation
Chip
L
PCB trace
C
f =1/(2p(LC)1/2)
L = 10 nH
C = 10 pF
f = ~500MHz
Z
R
Transmission line reflections
Package
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IO signals
• Direct voltage mode
– Simple driver (Large CMOS inverter)
– TTL, CMOS, LV-TTL, etc. Problems when Vdd of IC’s change.
– Large current peaks during transitions resulting in large oscillations
• Slew rated controlled
– Limiting output current during transitions
– Reduced oscillations
– (Reduced speed)
• Serial termination
– Driver must have same impedance as transmission line
(or external resistor)
– Only good for point to point
Imax
C
Imax
R=Z
Slew rate controlled
Z (50ohm)
Receiver
Sender
Serial termination
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• Current mode
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Switch current instead of voltage
Reduced current surge in power supply of driver
Reduced oscillations
External resistor to translate into voltage or
Low impedance measuring current directly
– Very good to drive transmission lines (similar to ECL)
I
Z
R
Parallel termination at the end
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• Differential
– Switch two opposite signals: signal and signal inverted
– Good for twisted pairs
• Prevents pickup from external noise sources
– Common mode of signal can be rejected
– Two pins per signal required
– High speed
Twisted pair
Differential receiver
Only sensitive to
differential amplitude
(common mode rejection)
Differential amplitude
Common mode
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• LVDS (Low Voltage swing Differential signaling)
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High speed (up to 250 MHz or higher)
Low voltage (independent of Vdd of different technologies)
Differential (twisted pairs)
Current mode
Terminated with same impedance as cable
Constant current in driver power supply (low noise)
I = > 2.5mA
Amplitude > 250 mV
(500mv differential)
R= ~100ohm
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Common mode = 1.25v
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Power supply
• Power supply current to synchronous circuits strongly correlated
to clock
• Large current surges when normal CMOS output drivers change
state
• Inductance in power supply lines in package.
• 10% - 50% of IC pins dedicated to power to ensure on-chip
power with low voltage drop and acceptable noise.
• Modern High end microprocessors needs tens of amperes at a
voltage of 1 – 2 volt !.
• IC packages with special power-ground planes and decoupling
capacitors
• Decoupling capacitors on chip
Power
pins
Clock
I
V
Board
capacitance
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Logic
Chip
capacitance
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Testing: Cost of finding failing chip
LEVEL
S p e cifica tio n
F A IL U R E M E CH A N IS M
F u n ctio n a lity, P e rfo rm a n ce
T e sta b ility, re lia b ility
In te ro p e ra b ility
D e sig n
P ro to typ e
W a fe r
C h ip
(M C M )
M o d u le
P R IC E
1000$
V e rifica tio n ,
Q u a lifica tio n ,
P ro d u ctio n m a rg in s
Y ie ld , sp e e d , n o ise , g a in
C u ttin g , b o n d in g
S o ld e rin g , E S D
D e sig n
ve rifica tio n
te stin g
1$
1 0 0 .0 0 0 $
100 $
G O LD
100K$ - ? $
(if n ot su fficie nt
d e sig n ve rifica ti on
pe rform e d)
1$
10$
100$
100 $
(S u b )
S yste m
A t cu sto me r
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C a b le s, co n n e cto rs
R e lia b ility o f co m p o n e n ts,
vib ra tio n s, co rro sio n ,
ra d ia tio n , h ig h vo lta g e
( p rice p e r d e sig n )
1000$
1 0 .0 0 0 $
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100 $
P ro d u ctio n
te stin g
(p rice p e r ch ip )
G O LD
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Design verification testing
(1 0 - 5 0 % o f to ta l d e ve lo p m e n t co sts)
D oe s m o de l co m ply
D o e s d e sig n ha ve sa m e
w ith sp e cifica tio n ?
b e ha vio u r a s m od e l ?
S p e cifica tio n
(te xt)
B e h a vio u ra l m o d e l
(V e rilo g , S p ice , e tc.)
D e sig n :
F u ll cu sto m ,
S ta n d a rd ce ll,
G a te a rra y
L o w q u a n tity
D o es d e sig n w ork ?
D o e s ch ip w o rk
a s sp e cifie d ?
( 50 % )
P ro d u ce d ch ip
D o e s ch ip w o rk in a p p lica tio n ?
(5 0 % * 5 0 % = 2 5 % )
D o e s sp e cifica tio n co m p ly
w ith a p p lica tio n ? (5 0 % )
S u fficie n t m a rg in s fo r
p ro d u ctio n va ria tio n s ?
(C an b e i m p rove d b y S ystem - IC
b eh a vio u ra l m od e llin g )
Is it te sta b le in p ro d u ctio n ?
Im p e rfe ct d e sign s a re o fte n
a ccep te d i n H E P if w a ys aro u nd
b ug s ca n b e fo un d .
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A p p lica tio n
R e lia b ility ?
H o w d o w e fin d o u t
w h a t’s w ro n g ?
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Production testing
W a fe r
(P ro d u ctio n te st p a tte rn d e ve lo p m e n t 5 - 2 5 % o f d e ve lo p m e n t co sts)
(P ro d u ctio n te st 2 0 - 5 0 % o f fin a l ch ip co st)
Fu n ctio na l te st:
fau lt co ve ra g e ,
stuck a t 0 /1
B u rn -in ?
B a re d ie
P a cka g e d
In te rn a l sp ee d te st:
clo ckin g spe e d
M arg in s ? (n oi se, m ea su rem e n t a ccu racy, e tc.)
T e m p e ratu re ? .
S u pp ly vo lta ge ?
E xtern a l lo ad s ?
MCM
A n a lo g p a ram e ters:
g ai n, n o ise ,
tim e co n stan ts,
p re cisio n , etc.
I/O le ve l te st:
o u tp ut le ve ls,
in p u t th re sho ld s
E xte rn al sp e e d te st:
se tu p tim e ,
h o ld tim e ,
d e la y
M o n ito rin g o f ra d ia tio n re sista n ce (d e stru ctive te st)
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Production yield
Y ie ld is ca lcu la te d fro m d e fe cts p e r m m 2 ( = e xp ( - A * D ) )
T yp ica l d e fe ct d e n sity is o f th e o rd e r o f 0 .0 0 5 - 0 .0 2 d e fe cts/m m 2
10 0.0
(m e m orie s ha ve red u n da n cy)
8 0.0
Y ield ( % )
V e ry h ig h p rod u ction vo lum e t ech n olo gy
61%
6 0.0
4 0.0
0 .005
0 .01
37 %
36 %
Typ ical A S I C te chn o lo g y
0.02
Lo w p rod u ction vo lum e t ech n olo gy
2 0.0
14 %
0.0
0.0
P rice o f 10 0 m m
5 0.0
2
1 00.0
A rea ( m m 2 )
2
ch ip co m p a re d to 5 0 m m ch ip :
20 0.0
1 00 m m /5 0 m m
2
2
x 0 .6 1/0 .3 7 = 3.4 ( D = 0.0 1 )
2
2
x 0 .3 6/0 .1 4 = 5.3 ( D = 0.0 2 )
1 00 m m /5 0 m m
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15 0.0
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Typical IC faults
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Reliability of integrated circuits
Failure rate
Infant mortality
Badly designed component
(electron migration, hot electron, corrosion, etc.)
Wear out
Time
1000 hours
10 years
Failing parts within first 1000 hours: 0.1 - 1 % (type, package, etc.)
Burn-in testing : Heating up chips to 125 deg. accelerates 1000 hours
period to approx. 24 hours.
Static: power supply connected.
Dynamic: Power + stimulation patterns.
Functional test: Power + stimulation patterns + test.
Temperature cycling: Continuous temperature cycling of chips to provoke
temperature gradient induced faults.
(Non matching thermal expansion coefficients).
Electrical stress: Operation at elevated supply voltage
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What to test
C o m b in a to ria l
S e q u e ntia l
M ixed a n a log /d ig ita l
N in p uts
N in pu ts
N in p uts
A /D
M sto ra g e e le m e nts
E xh a u stive te st ve cto rs: 2
N
E xh a u stive te st ve cto rs: 2
(N + M )
M stora g e e le m en ts
E xh a u stive te st ve cto rs: 2
p lu s an a lo g p a ram e te rs
1 0 0 M h z te ste r:
N = 3 2 ; te st tim e = 4 0 se co n d s.
N = 6 4 ; te st tim e = 6 .0 0 0 ye a rs
K n o w le d g e a b o u t to p o lo g y o f circu it m u st b e u se d to
re d u ce n u m b e r o f te st ve cto rs so th e y ca n b e g e n e ra te d
b y te ste r ( te ste r m e m o ry: 1 0 K - 1 0 M ).
A n a lo g a n d d ig ita l stim u li m u st b e g e n e ra te d fro m a tig h tly
syn ch ro n ise d syste m .
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(N + M )
Basic testing terms
C O N T R O L A B IL ITY : Th e e a s e o f c o n tro llin g th e s ta te o f
a n o d e in th e c irc u it.
O B S E R V A B IL IT Y : T h e e a s e o f o b s e rv in g th e s ta te o f a
n o d e in th e c irc u it
E x a m p le : 4 b it c o u n te r w ith c le a r
C o n tro l o f q 3 :
c lr
S e t lo w : p e rfo rm c le a r = 1 v e c to r
q3
q2
q1
q0
S e t h ig h : p e rfo rm c le a r + c o u n t to 1 0 0 0 B = 9 v e c to rs
T e s tin g a n o d e in a c irc u it
A : A p p ly s e q u e n c e o f te s t v e c to rs to c irc u it w h ic h s e ts n o d e to d e m a n d e d
s ta te .
B : A p p ly s e q u e n c e o f te s t v e c to rs to c irc u it w h ic h e n a b le s s ta te o f n o d e to
b e o b s e rv e d .
C : T h e o b s e rv in g te s t v e c to r s e q u e n c e m u s t n o t c h a n g e s ta te o f n o d e .
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Fault models
Fa ult typ es: F un ctiona l.
Tim ing .
A bstraction level: T ransisto r. (la yout)
G a te . (ne tlist)
M acro ( fu nction al blocks ).
D op in g
l
O p en
S hort
P aram e te r
R
gm
w
S ou rce
D ra in
G
D
D e la y
S
C
G a te
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1 /2
1
2
Vt
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Problematic faults at transistor level
Vo
T ran sfe r ch a ract eristic
Vo
Vi
X
A
Vi
A
0
0
1
1
B
0
1
1
0
X
1
1
0
1
A
0
1
1
0
B
0
0
1
1
X
1
1
0
1
A
0
0
1
1
B
0
1
1
0
X
1
1
0
0
B
P M O S stu ck o n
Vo
P M O S stu ck o pe n
Rpm os
Th resh o ld
Vi
Vo
Vi
C M O S log ic m a y b e c om e N M O S lo gic .
A
B
Id d q
C om bin a to ria l log ic m ay b ec o m e s eq u en tia l
V e cto r
1
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3
4
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Gate level (stuck at 0/1model)
S tu ck a t 0
S tu ck a t 1
O pen
B rid g e
Th e gate le vel stuck at 0 /1 is the d om in antly use d fa ult
m ode l fo r V L S I circu its, be cause o f its sim plicity.
Fa ult covera ge calcula te d by fa ult sim ulation a re alw ays
calcu lated using the stu ck at 0/1 m o del. O the r m ore co m plicated fault m od els are to com p ute inten sive for V LS I
designs.
F a u lt co ve ra g e =
N u m b e r o f fa u lts d e te cte d b y te st p a tte rn
T o ta l n u m b e r o f p o ssib le stu ck a t fa u lts in circu it
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Testability
F a u lt co ve ra g e
100 %
A
B
C
N u m b e r o f te st ve cto rs (te st ro u tin e s)
A : D e sig n m a d e w ith te sta b ility in m in d . ( ~1 te st ve cto r p e r g a te )
B : D e sig n m a d e w ith o u t te sta b ility in m in d b u t g o o d fa u lt co ve ra g e o b ta in e d
b y la rg e e ffo rt in m a kin g te st ve cto rs.
C : D e sig n ve ry d ifficu lt to te st e ve n u sin g la rg e e ffo rt in te st ve cto r g e n e ra tio n .
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Generation of test patterns
• Test vectors made by test engineer based on
functional description and schematics. Proprietary
test vector languages used to drive tester.
(over the wall)
• Test vectors made by design engineer on CAE
system. Subset of test patterns may be taken from
design verification simulations.
• Generated by Automatic Test Pattern Generators
( ATPG). Requires internal scan path
• Pseudo random generated test patterns.
• Fault simulation calculates fault coverage.
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Fault simulation
F a u lt co ve ra g e fo u n d b y fa u lt sim u la tio n s
T e st p a tte rn s
G ood
sim u la tio n m o d e l
R e fe re n ce
re sp o n se
S in g le fa u lt
sim u la tio n m o d e l
C o m p a re
re sp o n se
R e p e a t fo r a ll p o ssib le stu ck a t ze ro /o n e fa u lts
R e q u ire s lo n g sim u la tio n tim e s !.
T o g g le te st ( co u n ts h o w m a n y tim e s e a ch n o d e h a s ch a n g e d ) ca n b e u se d
to g e t a first im p re ssio n o f fa u lt co ve ra g e .
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Test development with increased complexity
C o st (tim e )
100 %
M ixe d a na lo g /d igi ta l
D e sig n
D ig ita l
T e st d e ve lo pm e n t
0 %
T o da y
C o m pl exity
(tim e )
T e sta b ility is d e cre a sin g
d ra stica lly w ith in cre a se d
in te g ra tio n le ve l
p ins/gate
1
0 .1
0 .0 1
0.0 01
SS I
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MS I
L SI
V LSI
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IC testers
H ig h sp e e d h ig h p in co u n t V L S I te ste rs a re ve ry e xp e n sive a n d co m p lica te d m a ch in e s.
(5 0 0 k$ - 1 0 M $ ).
Ve cto r sp e ed : 1 0 0 - 1 00 0 M H z,
Ve cto r d e pth : 3 2k - 1 G
Tim e re so lu tio n: 1 0 0 ps - 1 0p s
Pin co un t: 1 00 - 10 2 4
“Cheap”
= 500k$
+ M e a su re m e n ts o f D C ch a ra cte ristics
N o sta n d a rd M ixe d sig n a l te ste r e xists (m ixe d sig n a l te sts a re a lw a ys sp e cia l)
Te ste rs m u st be fa ster th an cu rre n t IC te ch no lo g y !.
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Scan Path testing
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Scan path testing
Im proving con tro lla bility/o bserva bility b y e nab lin g all
storag e no des to be con tro lle d/obse rve d via serial scan
p ath.
S ca n clo ck
S ca n d a ta in
L o g ic
L o g ic
S ca n d a ta o u t
T e st p rin cip le :
1 : E n a b le sca n m o d e a n d sca n in co n tro l d a ta .
2 : D isa b le sca n m o d e a n d clo ck ch ip o n e cycle .
3 : E n a b le sca n m o d e a n d sca n o u t o b se rvin g d a ta .
G e n e ra tio n o f te st ve cto rs: W ith th e h ig h co n tro lla b ility/o b se rva b ility th e te st ve cto rs
ca n b e g e n e ra te d a u to m a tica lly w ith a A T P G p ro g ra m .
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JTAG standard
IE E E 1 1 4 9 s ta n d a rd .
B o u n d a ry s c a n to te s t in te rc o n n e c t b e tw e e n c h ip s .
In te rn a l s c a n to te s t c h ip .
C o n tro l a n d s ta tu s o f b u ilt in s e lf te s t.
C h ip ID
M a n y c o m m e rc ia l c h ip s w ith J T A G s ta n d a rd im p le m e n te d :
P ro c e s s o rs , F P G A , e tc .
J TA G
T es t dat a o ut
C on tro lle r
T e st
r eg is t er
T e st
r eg is t er
A
(an a lo g )
T e st
r eg is t er
O utp uts
I npu ts
C
T e st
r eg is ter
T e st
r eg is t er
T e st
r eg is t er
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B
T e st
r eg is t er
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B o u n d a ry s c a n e n a b le s te s t o f d ig ita l b o a rd c o n n e c tio n s .
(a u to m a tic te s t g e n e ra tio n fr o m n e tlis t of b o a rd )
J T A G ID e n a b le s v e rific a tio n o f c o rre c t c o m p o n e n t ty p e .
E n a b le s a c c e s s to in te rn a l te s t fe a tu re s in c o m p o n e n ts .
T e s tin g c a n b e a ls o b e p e rfo rm e d in -s itu .
S m a ll a n d “c h e a p ” te s t s y s te m re q u ire d .
M a n y c o m m e rc ia l IC ’s n o w h a v e J T A G
(P ro c e s s o rs , F P G A ’s , e tc .)
S h o rt t o g ro u n d
IC 1
IC 3
S ol de r b r id ge
IC 2
O p en
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Built In Self Test (BIST)
D iffe re n t s c h e m e s o f b u ilt in (s e lf) te s t
In c lu d e te s t p a tte rn g e n e ra to r a n d
re s p o n s e c h e c k o n c h ip
M a k e s e lf c h e c k in g d u rin g o p e ra tio n
b y d u p lic a tin g a ll fu n c tio n s
L og ic
b lo c k 1
Lo g ic
un d er te s t
C o m pa re
re s p on s e
P a tte rn
g e ne ra to r
T es t
c o n tro l
L og ic
b lo c k 2
Re s p on s e
c he c k e r
G e n e ra te lo c a l c h e c k s u m s a n d c h e c k
w ith tra n s fo rm a tio n o f p re v io u s c h e c k s u m
Fa il
T ran s fo rm
Ch e c k s u m
Lo g ic
blo c k 1
C o m pa re
Ch e c k s u m
T ran s fo rm
Lo g ic
blo c k 2
C o m pa re
Ch e c k s u m
H a rd w a re o v e rh e a d !!
All commercial high end IC have extensive built in test features, but they are not documented for normal
users as they do not need to know for normal use and it is a part of the “secrets” of how to produce high quality ICs
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Good design practices
(If time allows)
Purpose of good design practices
•
•
•
•
•
•
•
Improve chance of chip working first time
Reduce (total) design time
Reduce development cost
Improved reliability
Improved production yield.
Follow vendor rules to get standard guarantees.
Some performance reduction may have to be
accepted
• (Be smart but not to smart)
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J.Christiansen/CERN
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Choice of technology
• Performance (speed, complexity)
• Design tools : Synthesis, P&R, etc.
– Cost of required tools
– Support for tools from which CAE tool supplier
• Libraries (gates, adders, RAM, ROM, PLL’s, PCI,
ADC, etc.)
• Development costs
– Full engineering run: NRE (several hundred thousand
dollars)
– Multi Project Wafer (MPW)
• Life time of technology
– Modern CMOS only have a life time of ~5 years
• Production
– Price as function of volume
– Production testing
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J.Christiansen/CERN
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Well planned design hierarchy
• The hierarchy of a design is the base for the whole
design process.
– Define logical functional blocks
– Minimize connections between branches of hierarchy
– Keep in mind that Hierarchy is going to be used for
synthesis, simulation, Place & route, testing, etc.
• Define architecture in a top-down approach
• Evaluate implementation and performance of critical
blocks to determine if architecture must be changed.
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J.Christiansen/CERN
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Synchronous design
• All flip-flops clocked with same clock.
• Only use clocked flip-flops
– no RS latches, cross coupled gates, J-K flip-flops, etc.
• No asynchronous state machines
• No self-timed circuits
d
d
q
d
q
Logic
q
Logic
Clock
Clock
Sb
Rb
Trieste 2006
d
q
Q
Rb
Sb
Q
0
0
1
0
1
0
1
0
1
1
1
Q*
Race condition
Legal transitions
J.Christiansen/CERN
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Clock gating
• Clock gating has the potential of significant power
savings disabling clocks to functions not active.
• Clock gating introduces a significant risk of
malfunctions caused by glitches when
enabling/disabling clock
d
q
Enable
And
d
q
Clock
Clock
Enable
Gated clock
Edge delayed
Trieste 2006
Glitch
J.Christiansen/CERN
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Clock distribution
• Even in synchronous designs, race conditions can occur if clock
not properly distributed
– Flip-flops have set-up and hold time restrictions
– Clocks may not arrive at same time to different flip-flops.
– Especially critical for shift registers where no logic delays exists
between neighbor flip-flops.
– Clock distribution must be very - very carefully designed and
dummy logic may be needed between flip-flops.
d
d
q
d
q
q
Dummy
delay
X 10
d
q
X 20
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J.Christiansen/CERN
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Resets
• Asynchronous resets must still be synchronized to
clock to insure correct start when reset released
• Synchronous reset made by simple gating of input
Asynchronous reset
d
Clock
Synchronous reset
q
Reset
R
d
Reset
q
Clock
Reset
Recovery
time
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J.Christiansen/CERN
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Interface to asynchronous world
• It is in many applications necessary to interface to
circuits not running with the same clock.
– Natural signals are asynchronous
– Signals between different systems
– Many chips today uses special internal clocks (e.g.. X 2)
• Asynchronous signals must be synchronized
– Synchronizers are sensitive to meta-stability
– Use double or triple synchronizers
Async.
d
q
Delay
Voltage
Double synchronizer
Clock
Async.
q
d
q
Normal
delay
Clock
Data
0
Trieste 2006
d
Time
difference
J.Christiansen/CERN
Clock
Time
50
On-chip data busses
• Data busses are often required to exchange data
between many functional units.
– Insure that only one driver actively driving bus
Also before chip have been properly initialized
Bus drivers are often power full and a bus contention may be destructive.
– Insure that bus is never left in a tri-state state.
A floating bus may result in significant short circuit currents in receivers
• Always have one source driving the bus
• Use special bus retention generators.
Bus contention control
Vdd
Ivdd
In
Bus retention
Vin
Trieste 2006
J.Christiansen/CERN
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Mixed signal designs
• Extreme care must be taken in mixed analog - digital integrated
circuits to limit coupling to the sensitive analog part.
– Separate power supplies for analog and digital
• Best powering scheme for sensitive mixed signal designs depends strongly on
used technology:
– High conductive substrate
– Low conductive substrate
– Silicon on Insulator (SOI)
– Guard ring connected to ground around analog blocks
Efficiency of this depends a lot on substrate type.
– Separate test of analog and digital (scan path)
– Use differential analog circuits to reject common mode noise
• If not using differential analog one is most likely in trouble
– Be careful with digital outputs which may inject noise into analog
part (use if possible differential outputs)
• Difficult but can be done
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J.Christiansen/CERN
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Simulation
• Simulation is the most important tool to Ensure
correct behavior of IC.
– Circuit must be simulated in all possible operating modes
– Digital simulator output should not only be checked by
looking at waveforms
– Circuit must be simulated under all process and operating
conditions (corner parameters)
•
•
•
•
•
•
Best case:
-20 deg. , good process, Vdd + 10%
x ~0.5
Typical:
20 deg., typical process, Vdd
x 1.0
Worst case:
100 deg., bad process, Vdd - 10%
x ~2.0
Worst N - best P: NMOS bad process, PMOS good process (analog)
Best N - worst P: NMOS good process, PMOS bad process (analog)
Plus many other combinations of different device parameters
(which combination is the worst for my circuit ?)
• IC designers spend most of their time simulating and
writing simulation environments.
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J.Christiansen/CERN
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Testing
• One can “never” put to much test facilities in chips.
• Put scan path where ever possible.
• Have special test outputs which can be used for
monitoring of critical circuits.
• Put internal test pads on special tricky analog circuits.
• If in doubt about critical parameters of design make it
programmable if possible.
• Do not forget about production testing.
• Do not make a redesign before problems with current
version well understood.
• Most designs needs some kind of redesign.
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J.Christiansen/CERN
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If you make IC design like this
You may end up like this
Or like this
When something is wrong it is very hard to find the exact cause of the problem.
Design changes are expensive and introduces significant delays
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J.Christiansen/CERN
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