Transcript Technology Roadmap INTEL Processors 2014

Technology Roadmap
of
INTEL’s Processors
July 2014
Table of Contents
Intel’s product line from Pentium to Ivy Bridge
Above 100 nm node (Gate-First)
Sub-100 nm nodes:
90 nm and 65 nm (Gate-First)
45 nm, 32nm and 22nm (Gate-Last, high-k & metal gates)
Parameters related to “Technology Node”
Contacted Gate Pitch
6T SRAM Cell Size
Metal 1 Pitch
Future
What to expect NEXT?
Technology Roadmap Intel Processors 2014
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Above 100 nm, Gate-First: Package (top & bottom)
0.35 µm
Intel Pentium
Microprocessor (200 MHz)
Technology Roadmap Intel Processors 2014
0.18 µm
Intel III Microprocessor
“Coppermine” (450 MHz)
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0.13 µm
Intel III Microprocessor
“Tualatin” (1.26 GHz)
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Above 100 nm, Gate-First: Die and Die markings
0.35 µm
Intel Pentium
Microprocessor (200 MHz)
0.18 µm
Intel III Microprocessor
“Coppermine” (450 MHz)
0.13 µm
Intel III Microprocessor
“Tualatin” (1.26 GHz)
7.1 mm x 11.1 mm = 79 mm2
10.8 mm x 12.6 mm = 136.1 mm2
10.3 mm x 12.3 mm = 126.7 mm2
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Above 100 nm, Gate-First: SRAM at gate level
0.35 µm
Intel Pentium
Microprocessor (200 MHz)
0.18 µm
Intel III Microprocessor
“Coppermine” (450 MHz)
0.13 µm
Intel III Microprocessor
“Tualatin” (1.26 GHz)
All the SRAMS: P+ diffusions of the pull-down transistors have an “H” shape and each one is shared by
two SRAM cells
Wordline and pull-down are 90˚ at each other and this consumes lot of space
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Above 100 nm: Critical Parameters
Parameters
0.35 µm Node
0.18 µm Node
0.13 µm Node
Die size
NMOS gate length
PMOS gate length
Minimum metal 1 pitch
Gate oxide thickness
Contacted gate pitch
Silicide
Metallizations levels
SRAM cell size
136 mm2
335 nm
330 nm
950 nm
5 nm
1480 nm
TiSi
4 (A1)
18.1 µm2
126.7 mm2
120 nm
130 nm
750 nm
2.5 nm
760 nm
CoSi
6 (A1)
6 µm2
79 mm2
70 nm
70 nm
360 nm
1.9 nm
510 nm
CoSi
6 (Cu)
3.25 µm2
The devices before 0.35 µm are not taken because previous two generations (0.6 µm
and 0.8 µm) used BiCMOS process
The 0.25 µm node has been omitted to avoid clutter
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Above 100 nm: Summary
In four generations (0.35 µm, 0.25 µm, 0.18 µm, 0.13 µm):
The die area shrunk from 136 to 79 mm2
The gate length reduced from 335 nm to 70 nm
The metal 1 pitch scaled down from 950 nm to 360 nm
The SRAM cell size decreased from 18.1 µm2 to 3.25 µm2
Not all parameters scaled in the same proportion
Intel moved towards sub 100 nm nodes with process-integration experience in
Cu-interconnects and low-k materials
By 130 nm node all the processors had a clock frequency in the range of 3 GHz
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Sub 100 nm, Gate-First: Package (Top & Bottom)
90 nm
Intel Pentium IV, “Prescott”
(3 GHz)
65 nm
Intel Dual Core, “Xeon”
(3 GHz)
90 nm and 65 nm are two generations
below 100 nm nodes, which used
conventional gate structure with poly
for gate electrode and oxide for gate
dielectric
65 nm node was essentially a shrink of
90 nm
The most innovative part in 65 nm
node was the introduction of dual
core architecture
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Sub 100 nm, Gate-First: Die and Die markings
90 nm
Intel Pentium IV, “Prescott”
(3 GHz)
10.8 mm x 10.34 mm =
112 mm2
Technology Roadmap Intel Processors 2014
65 nm
Intel Dual Core, “Xeon”
(3 GHz)
13.4 mm x 10.4 mm =
142 mm2
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Sub 100 nm, Gate-First: SRAM at gate level
90 nm
Intel Pentium IV, “Prescott”
(3 GHz)
65 nm
Intel Dual Core, “Xeon”
(3 GHz)
The SRAM cell at diffusion changed from H_O structure to continuous regions of P-well
for NMOS transistors and I shaped regions of N-well for PMOS transistors
Intel 65 nm node is 2nd generation of strain silicon technology
65 nm node adopted the same uniaxial strained approach as 90 nm node
Epitaxial SiGe film was employed for PMOS source-drains in 65 nm and 90 nm node
Up to 65 nm node, single patterning was only used
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Sub 100 nm, Gate-Last: Package (Top &Bottom)
45 nm
Intel Core
2TM Extreme,
(3 GHz)
Technology Roadmap Intel Processors 2014
22 nm
32 nm Intel Dual Core,
“Penryn” “Clarkdale/Westemere” Intel Quadcore, “IVY Bridge” (3.3
GHz)
(3 GHz)
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Sub 100 nm, Gate-Last: Die and Die markings
45 nm
TM
Intel Core 2 Extreme, “Penryn”
(3 GHz)
32 nm Intel Dual Core,
“Clarkdale/Westemere”
(3 GHz)
22 nm
Intel Quadcore, “IVY Bridge” (3.3
GHz)
12.2 mm x 8.5 mm =
104 mm2
19.6 mm x 8.0 mm =
112 mm2
9.2 mm x 8.2 mm = 75.4
mm2
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Sub 100 nm, Gate-Last:
45 nm
Intel Core 2TM Extreme, “Penryn”
(3 GHz)
SRAM at gate level
32 nm Intel Dual Core,
“Clarkdale/Westemere”
(3 GHz)
22 nm
Intel Quadcore, “IVY Bridge” (3.3
GHz)
The 6T SRAM cell has been the vehicle to define technology nodes
Cross couple PMOS and NMOS metal gates are connected at the side of the metal gate.
45 nm node uses double patterning with 193 nm dry lithography
32 nm node uses double patterning with 193 nm immersion lithography
22 nm node introduces fins and uses double patterning with 193 nm immersion lithography
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Sub 100 nm, Gate-Last:
Summary
Intel’s 45 nm process is the first to incorporate high-k metal gate (HKMG) technology. Their
innovative process protects the high-k gate dielectric from polysilicon etch by depositing a TiN top
interface layer (TIL) before polysilicon deposition and patterning.
PMOS channel stress is enhanced by removing the polysilicon dummy gates which is an enabling
factor of the replacement metal gate process Intel used for the first time double patterning based
on 193 nm dry lithography for critical layers and at the transistor gate level. Intel’s 32 nm was
essentially a shrink of 45 nm node with the exception that immersion lithography was used.
As of today, 2014, Intel is the only manufacturer to use a FinFET for its transistors. Intel 22 nm
replaced the traditional 2-D planar MOS transistor with a gate that is wrapped around a thin
three-dimensional silicon fin that rises up vertically from the silicon substrate . A thin high-k
dielectric separates the silicon fin from the metal gate on each of the three sides of the fin
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Sub 100 nm, Gate-Last:
Technology Roadmap Intel Processors 2014
Graphical Summary
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Sub 100 nm, Gate-Last:
Critical Dimensions (Logic)
Node
90 nm
65 nm
45 nm
Lithography
248 nm dry
193 nm dry
193 nm dry
Process
32 nm
22 nm
193 nm immersion + 193 nm immersion +
double patterning
double patterning
SiGe is used to strain
SiGe_PMOS;
Tri-gate transistor;
a silicon channel;
SiGe for PMOS; Poly SiGe for PMOS; Metal eSi_NMOS; Metal
SiG3_PMOS;
tensile nitride layer gates; W contact, M1 gates with High-K; W gates with high-K, M0 eSi_NMOS; Metal
for NMOS channel;
in Cu
contact; M1 in Cu
level in Cu; W
gates, M0 level in W;
Ni-Si replaces Co-Si
contact; M1 in Cu W contact; M1 in Cu
Minimum Contacted
Gate Pitch (nm)
310
220
160
113
90
Minimum Gate
Length (nm)
45
36
45
34
25
Minimum Metal 1
Pitch (nm)
220
210
150
113
90
90 nm and 45 nm have the same gate-length
65 nm and 32 nm have the same gate-length
Gate length is not an accurate parameter for defining technology node for devices below 100
nm node
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Sub 100 nm, Gate-Last: Critical Dimensions (SRAM)
The 32 nm node introduced the metal 0 level and changed the wiring position of bitlines (BL),
Wordlines (WL), Vss and Vdd lines and improved slightly the width/length (W/L) ratio of transistors
The SRAM in 22 nm node kept the same wiring configuration for BL, WL, Vdd and Vss, as
in 32 nm node but by introducing Tri-Gate (FinFET) structure improved W/L ratio
Generally, the widths of pull down transistors are greater than the widths of access transistors. The current ratio
of I PD /I AC reflecting geometric device dimension is known as beta ratio. A higher beta ratio reflects higher cell
stability
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Table of Contents
Intel’s product line from Pentium to Ivy Bridge
Above 100 nm node (Gate-First)
Sub-100 nm nodes:
90 nm and 65 nm (Gate-First)
45 nm, 32nm and 22nm (Gate-Last, high-k & metal gates)
Parameters related to “Technology Node”
Contacted Gate Pitch
6T SRAM Cell Size
Metal 1 Pitch
Future
What to expect NEXT?
Technology Roadmap Intel Processors 2014
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Parameters related to “Technology Node”
For advanced nodes “Gate-Length” is not a reliable parameter for defining technology node
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Parameters related to “Technology Node”
The “Contacted Gate Pitch” takes in account the gate length and the minimum litho-features,
thus reflects the actual technology node
“Contacted Gate Pitch” decreases by 0.7 every two years, following Intel’s “Tick Tock” scheme
Every alternate year Intel develops a new process technology and the following year a new
miro-architecture, (Tick / Tock scheme)
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Parameters related to “Technology Node”
The “square root of 6T-SRAM cell area” is linear with technology node and is an accurate method
to determine the technology node
Intel 22 nm has 0.092 µm2 SRAM cell for high density applications but our analysis did not locate
these cells, only 0.108 µm2 SRAM cell for low voltage applications was found in reverse
engineering.
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Parameters related to “Technology Node”
The “Metal 1 Pitch” is also indicative of the technology node but not very accurate
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Table of Contents
Intel’s product line from Pentium to Ivy Bridge
Above 100 nm node (Gate-First)
Sub-100 nm nodes:
90 nm and 65 nm (Gate-First)
45 nm, 32nm and 22nm (Gate-Last, high-k & metal gates)
Parameters related to “Technology Node”
Contacted Gate Pitch
6T SRAM Cell Size
Metal 1 Pitch
Future
What to expect NEXT?
Technology Roadmap Intel Processors 2014
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What is coming NEXT?
Intel has developed both CPU and SoC processes for its 45 nm, 32 nm and 22 nm
technology nodes
SoC products usually incorporate a variety of devices that are often not seen in
regular CPU products
Intel will use the 22 nm technology node platform and diversify for different products
Intel is not pursuing only high performance, but developing process and architectures
for wider range of products varying from server-market to mobile market
This wide variety of products requires different design at one particular technology
node
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What is coming NEXT?
Different chips with different designs are available at 22 nm technology, for
example:
Ivy Bridge ( CPU);
Haswell (Soc);
Bay Trail (for tablets, Atom Z300series)
Intel 22 nm
Ivy Bridge
Technology Roadmap Intel Processors 2014
Intel 22 nm
Haswell
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Bay Trail 22 nm
ATOM Z300
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What is coming NEXT?
Generation of High-K and Metal Gates with “Gate-Last” process
Most likely bulk FinFET will be used for 14 nm node
EUV will probably be used for sub 10 nm nodes
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