Transcript CMOS FAB Process

VLSI Design
Lecture 2: Basic Fabrication Steps and
Layout
Mohammad Arjomand
CE Department
Sharif Univ. of Tech.
Adapted with modifications from Harris’s lecture notes
Outline
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How to make a transistor or a gate
 Cross-section
 Top view (masks)
 Fabrication process
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Layout
Design rules
Standard cell layouts
Stick Diagrams
Modern VLSI Design 4e: Chapter 2
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Our technology
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We will study a generic 180 nm technology (SCMOS
rules).
 Assume 1.2V supply voltage.
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Parameters are typical values.
Parameter sets/Spice models are often available for 180
nm, harder to find for 90 nm.
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Fabrication services
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Educational services:
 U.S.: MOSIS (has defined SCMOS rules)
 EC: EuroPractice
 Taiwan: CIC
 Japan: VDEC
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Foundry = fabrication line for hire.
 Foundries are major source of fab capacity today.
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Silicon Lattice
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Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors
Modern VLSI Design 4e: Chapter 2
Si
Si
Si
Si
Si
Si
Si
Si
Si
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Dopants
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Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V (Arsenic, Phosphorus): extra electron (n-type)
Group III (Boron): missing electron, called hole (p-type)
Si
Si
Si
Si
Si
Si
As
Si
Si
B
Si
Si
Si
Si
Si
-
+
Modern VLSI Design 4e: Chapter 2
+
-
Si
Si
Si
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p-n Junctions
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A junction between p-type and n-type semiconductor
forms a diode.
Current flows only in one direction
N-Diff
cathode
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P-Diff
anode
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Fabrication processes
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IC built on silicon substrate:
 some structures diffused into substrate;
 other structures built on top of substrate.
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Substrate regions are doped with n-type and p-type
impurities. (n+ = heavily doped)
Wires made of polycrystalline silicon (poly), multiple
layers of aluminum (metal).
Silicon dioxide (SiO2) is insulator.
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CMOS Fabrication
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CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or
etched
Easiest to understand by viewing both top and crosssection of wafer in a simplified manufacturing process
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CMOS Inverter
VDD
A
Y
A
Y
GND
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Inverter Cross-section
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Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
A
GND
VDD
Y
SiO2
n+ diffusion
n+
n+
p+
p+
n well
p substrate
nMOS transistor
Modern VLSI Design 4e: Chapter 2
p+ diffusion
polysilicon
metal1
pMOS transistor
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Slide 11 of 50
Well and Substrate Taps
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Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
Use heavily doped well and substrate contacts / taps
A
GND
VDD
Y
p+
n+
n+
p+
p+
n+
n well
p substrate
substrate tap
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well tap
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Inverter Mask Set
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Transistors and wires are defined by masks
Cross-section taken along dashed line
A
Y
GND
VDD
nMOS transistor
pMOS transistor
well tap
substrate tap
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Slide 13 of 50
Detailed Mask Views
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Six masks
n well
 n-well
 Polysilicon
 n+ diffusion
Polysilicon
 p+ diffusion
n+ Diffusion
 Contact
p+ Diffusion
 Metal
Contact
Metal
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Fabrication Steps
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Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
 Cover wafer with protective layer of SiO2 (oxide)
 Remove layer where n-well should be built
 Implant or diffuse n dopants into exposed wafer
 Strip off SiO2
p substrate
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Oxidation
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Grow SiO2 on top of Si wafer
 900 – 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
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Photoresist
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Spin on photoresist
 Photoresist is a light-sensitive organic polymer
 Softens where exposed to light
Photoresist
SiO2
p substrate
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Slide 17 of 50
Lithography
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Expose photoresist through n-well mask
Strip off exposed photoresist
Photoresist
SiO2
p substrate
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Etch
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Etch oxide with hydrofluoric acid (HF)
 Seeps through skin and eats bone; nasty stuff!!!
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Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
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Strip Photoresist
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Strip off remaining photoresist
 Use mixture of acids called piranah etch
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Necessary so resist doesn’t melt in next step
SiO2
p substrate
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n-well
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n-well is formed with diffusion or ion implantation
Diffusion
 Place wafer in furnace with arsenic gas
 Heat until As atoms diffuse into exposed Si
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Ion Implanatation
 Blast wafer with beam of As ions
 Ions blocked by SiO2, only enter exposed Si
SiO2
n well
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Slide 21 of 50
Strip Oxide
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Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
n well
p substrate
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Slide 22 of 50
Polysilicon
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Deposit very thin layer of gate oxide
 < 20 Å (6-7 atomic layers)
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Chemical Vapor Deposition (CVD) of silicon layer
 Place wafer in furnace with Silane gas (SiH4)
 Forms many small crystals called polysilicon
 Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate
Modern VLSI Design 4e: Chapter 2
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Slide 23 of 50
Polysilicon Patterning
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Use same lithography process to pattern polysilicon
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
Modern VLSI Design 4e: Chapter 2
Sharif University of Technology
Slide 24 of 50
Self-Aligned Process
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Use oxide and masking to expose where n+ dopants
should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well
contact
n well
p substrate
Modern VLSI Design 4e: Chapter 2
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Slide 25 of 50
N-diffusion
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Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
n+ Diffusion
n well
p substrate
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Slide 26 of 50
N-diffusion cont.
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Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
n+
n+
n+
n well
p substrate
Modern VLSI Design 4e: Chapter 2
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Slide 27 of 50
N-diffusion cont.
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Strip off oxide to complete patterning step
n+
n+
n+
n well
p substrate
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Sharif University of Technology
Slide 28 of 50
P-Diffusion
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Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
p+
n+
n+
p+
p+
n+
n well
p substrate
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Contacts
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Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Contact
Thick field oxide
p+
n+
n+
p+
p+
n+
n well
p substrate
Modern VLSI Design 4e: Chapter 2
Sharif University of Technology
Slide 30 of 50
Metalization
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Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
Metal
Metal
Thick field oxide
p+
n+
n+
p+
p+
n+
n well
p substrate
Modern VLSI Design 4e: Chapter 2
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Slide 31 of 50
Simple cross section
SiO2
metal3
metal2
metal1
transistor
via
poly
n+
Modern VLSI Design 4e: Chapter 2
p+
n+
substrate
substrate
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Photolithography
Mask patterns are put on wafer using photo-sensitive
material:
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Slide 33 of 32
Process steps
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First place tubs (wells) to provide properly-doped
substrate for n-type, p-type transistors.
a twin-tub process:
p-tub
n-tub
substrate
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Slide 34 of 32
Process steps, cont’d.
Pattern polysilicon before diffusion regions:
poly
gate oxide
p-tub
Modern VLSI Design 4e: Chapter 2
poly
n-tub
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Slide 35 of 32
Process steps, cont’d
Add diffusions, performing self-masking:
poly
n+
p-tub
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poly
n+
p+
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n-tub
p+
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Process steps, cont’d
Start adding metal layers:
metal 1
metal 1
vias
poly
n+
p-tub
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n+
poly
p+
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n-tub
p+
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