Transcript CMOS FAB Process-2x

VLSI Design
Lecture 2: Basic Fabrication Steps and
Layout
Mohammad Arjomand
CE Department
Sharif Univ. of Tech.
Adapted with modifications from Harris’s lecture notes
Outline

How to make a transistor or a gate
 Cross-section
 Top view (masks)
 Fabrication process

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
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Layout
Design rules
Standard cell layouts
Stick Diagrams
Modern VLSI Design 4e: Chapter 2
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Slide 2 of 50
Our technology

We will study a generic 180 nm technology (SCMOS
rules).
 Assume 1.2V supply voltage.


Parameters are typical values.
Parameter sets/Spice models are often available for 180
nm, harder to find for 90 nm.
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Slide 3 of 50
Fabrication services

Educational services:
 U.S.: MOSIS (has defined SCMOS rules)
 EC: EuroPractice
 Taiwan: CIC
 Japan: VDEC

Foundry = fabrication line for hire.
 Foundries are major source of fab capacity today.
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Slide 4 of 50
Silicon Lattice
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Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors
Modern VLSI Design 4e: Chapter 2
Si
Si
Si
Si
Si
Si
Si
Si
Si
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Dopants
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Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V (Arsenic, Phosphorus): extra electron (n-type)
Group III (Boron): missing electron, called hole (p-type)
Si
Si
Si
Si
Si
Si
As
Si
Si
B
Si
Si
Si
Si
Si
-
+
Modern VLSI Design 4e: Chapter 2
+
-
Si
Si
Si
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p-n Junctions
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A junction between p-type and n-type semiconductor
forms a diode.
Current flows only in one direction
N-Diff
cathode
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P-Diff
anode
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Slide 7 of 50
Fabrication processes

IC built on silicon substrate:
 some structures diffused into substrate;
 other structures built on top of substrate.
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Substrate regions are doped with n-type and p-type
impurities. (n+ = heavily doped)
Wires made of polycrystalline silicon (poly), multiple
layers of aluminum (metal).
Silicon dioxide (SiO2) is insulator.
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Slide 8 of 50
CMOS Fabrication
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CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or
etched
Easiest to understand by viewing both top and crosssection of wafer in a simplified manufacturing process
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Slide 9 of 50
CMOS Inverter
VDD
A
Y
A
Y
GND
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Slide 10 of 50
Inverter Cross-section


Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
A
GND
VDD
Y
SiO2
n+ diffusion
n+
n+
p+
p+
n well
p substrate
nMOS transistor
Modern VLSI Design 4e: Chapter 2
p+ diffusion
polysilicon
metal1
pMOS transistor
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Slide 11 of 50
Well and Substrate Taps
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Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
Use heavily doped well and substrate contacts / taps
A
GND
VDD
Y
p+
n+
n+
p+
p+
n+
n well
p substrate
substrate tap
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well tap
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Inverter Mask Set
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Transistors and wires are defined by masks
Cross-section taken along dashed line
A
Y
GND
VDD
nMOS transistor
pMOS transistor
well tap
substrate tap
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Slide 13 of 50
Detailed Mask Views

Six masks
n well
 n-well
 Polysilicon
 n+ diffusion
Polysilicon
 p+ diffusion
n+ Diffusion
 Contact
p+ Diffusion
 Metal
Contact
Metal
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Slide 14 of 50
Fabrication Steps
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Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
 Cover wafer with protective layer of SiO2 (oxide)
 Remove layer where n-well should be built
 Implant or diffuse n dopants into exposed wafer
 Strip off SiO2
p substrate
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Slide 15 of 50
Oxidation

Grow SiO2 on top of Si wafer
 900 – 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
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Slide 16 of 50
Photoresist

Spin on photoresist
 Photoresist is a light-sensitive organic polymer
 Softens where exposed to light
Photoresist
SiO2
p substrate
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Slide 17 of 50
Lithography
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Expose photoresist through n-well mask
Strip off exposed photoresist
Photoresist
SiO2
p substrate
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Slide 18 of 50
Etch
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Etch oxide with hydrofluoric acid (HF)
 Seeps through skin and eats bone; nasty stuff!!!

Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
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Slide 19 of 50
Strip Photoresist
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Strip off remaining photoresist
 Use mixture of acids called piranah etch

Necessary so resist doesn’t melt in next step
SiO2
p substrate
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Slide 20 of 50
n-well
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
n-well is formed with diffusion or ion implantation
Diffusion
 Place wafer in furnace with arsenic gas
 Heat until As atoms diffuse into exposed Si

Ion Implanatation
 Blast wafer with beam of As ions
 Ions blocked by SiO2, only enter exposed Si
SiO2
n well
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Slide 21 of 50
Strip Oxide
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Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
n well
p substrate
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Slide 22 of 50
Polysilicon

Deposit very thin layer of gate oxide
 < 20 Å (6-7 atomic layers)

Chemical Vapor Deposition (CVD) of silicon layer
 Place wafer in furnace with Silane gas (SiH4)
 Forms many small crystals called polysilicon
 Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate
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Slide 23 of 50
Polysilicon Patterning
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Use same lithography process to pattern polysilicon
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
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Slide 24 of 50
Self-Aligned Process
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Use oxide and masking to expose where n+ dopants
should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well
contact
n well
p substrate
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Slide 25 of 50
N-diffusion
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Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
n+ Diffusion
n well
p substrate
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Slide 26 of 50
N-diffusion cont.
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Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
n+
n+
n+
n well
p substrate
Modern VLSI Design 4e: Chapter 2
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Slide 27 of 50
N-diffusion cont.

Strip off oxide to complete patterning step
n+
n+
n+
n well
p substrate
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Sharif University of Technology
Slide 28 of 50
P-Diffusion

Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
p+
n+
n+
p+
p+
n+
n well
p substrate
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Slide 29 of 50
Contacts
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Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Contact
Thick field oxide
p+
n+
n+
p+
p+
n+
n well
p substrate
Modern VLSI Design 4e: Chapter 2
Sharif University of Technology
Slide 30 of 50
Metalization
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Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
Metal
Metal
Thick field oxide
p+
n+
n+
p+
p+
n+
n well
p substrate
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Slide 31 of 50
Simple cross section
SiO2
metal3
metal2
metal1
transistor
via
poly
n+
Modern VLSI Design 4e: Chapter 2
p+
n+
substrate
substrate
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Slide 32 of 32
Photolithography
Mask patterns are put on wafer using photo-sensitive
material:
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Slide 33 of 32
Process steps

First place tubs (wells) to provide properly-doped
substrate for n-type, p-type transistors.
a twin-tub process:
p-tub
n-tub
substrate
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Slide 34 of 32
Process steps, cont’d.
Pattern polysilicon before diffusion regions:
poly
gate oxide
p-tub
Modern VLSI Design 4e: Chapter 2
poly
n-tub
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Slide 35 of 32
Process steps, cont’d
Add diffusions, performing self-masking:
poly
n+
p-tub
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poly
n+
p+
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n-tub
p+
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Process steps, cont’d
Start adding metal layers:
metal 1
metal 1
vias
poly
n+
p-tub
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n+
poly
p+
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n-tub
p+
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Transistor structure
n-type transistor:
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0.25 micron transistor (Bell Labs)
gate oxide
silicide
source/drain
poly
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Slide 39 of 32
Transistor layout
n-type (tubs may vary):
L
w
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Slide 40 of 32
NMOS Transistor
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Four terminals: gate, source, drain, body
Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS) capacitor
» Even though gate is
no longer made of metal
Source
Gate
Drain
Polysilicon
SiO2
n+
n+
p
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bulk Si
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NMOS Operation
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Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source
Gate
Drain
Polysilicon
SiO2
0
n+
n+
S
p
Modern VLSI Design 4e: Chapter 2
D
bulk Si
Sharif University of Technology
Slide 42 of 32
NMOS Operation (cont’d.)
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When the gate is at a high voltage:
–
–
–
–
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from source
through channel to drain, transistor is ON
Source
Gate
Drain
Polysilicon
SiO2
1
n+
n+
S
p
Modern VLSI Design 4e: Chapter 2
D
bulk Si
Sharif University of Technology
Slide 43 of 32
PMOS Transistor

Similar, but doping and voltages reversed
–
–
–
–
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
Source
Gate
Drain
Polysilicon
SiO2
p+
p+
n
Modern VLSI Design 4e: Chapter 2
bulk Si
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Slide 44 of 32
Drain current characteristics
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Slide 45 of 32
Drain current

Linear region (Vds < Vgs - Vt):
– Id = k’ (W/L)[(Vgs - Vt)Vds - 0.5 Vds2]

Saturation region (Vds ≥ Vgs - Vt):
– Id = 0.5k’ (W/L)(Vgs - Vt) 2
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Slide 46 of 32
180 nm transconductances
Typical values:
 n-type:
– kn’ = 170 A/V2
– Vtn = 0.5 V

p-type:
– kp’ = 30 A/V2
– Vtp = -0.5 V
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Slide 47 of 32
Current through a transistor
Use 180 nm parameters. Let W/L = 3/2. Measure at
boundary between linear and saturation regions.
 Vgs = 0.7V:
Id = 0.5k’(W/L)(Vgs-Vt)2 = 0.5(170 A/V2)(3/2)(0.7-0.5)2 = 5.1
A

Vgs = 1.2V:
Id = 62 A
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Slide 48 of 32
Basic transistor parasitics
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Gate to substrate, also gate to source/drain.
Source/drain capacitance, resistance.
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Slide 49 of 32
Basic transistor parasitics, cont’d
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Gate capacitance Cg. Determined by active area.
Source/drain overlap capacitances Cgs, Cgd.
Determined by source/gate and drain/gate overlaps.
Independent of transistor L.
– Cgs = Col W

Gate/bulk overlap capacitance.
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Slide 50 of 32
Latch-up
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CMOS ICs have parastic silicon-controlled rectifiers
(SCRs).
When powered up, SCRs can turn on, creating lowresistance path from power to ground. Current can
destroy chip.
Early CMOS problem. Can be solved with proper
circuit/layout structures.
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Slide 51 of 32
Parasitic SCR structure
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There exist parasitic bipolar transistors (pnp and npn) in a CMOS
structure.
Additionally, the well and substrate have resistances RW and RS,
respectively.
Twin tub
n tub
Rwell
A
Vwell
GND
p+
Vsub
Rsub
Rsub
substrate tap
Modern VLSI Design 4e: Chapter 2
n+
VDD
Y
n+
p substrate
p+
n well
p+
n+
Rwell
Vwell
Vsub
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well tap
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Parasitic SCR
circuit
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I-V behavior
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Slide 53 of 32
Solution to latch-up
Use tub ties to connect tub to power rail. Use enough to
create low-voltage connection.
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Slide 54 of 32
Tub tie layout
p+
metal (VDD)
p-tub
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Slide 55 of 32