Transcript WP3: 3D Interconnection and post processing

Talent
WP3: Development of radiation-hard high-density
electronics and interconnection with sensors
N. Wermes
TALENT Network Annual Meeting
CERN, Nov. 20, 2013
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Norbert Wermes – University of Bonn – Nov 20 - 2013
WP3 Objectives
1. Optical data transmission (Wuppertal)
2. 3D integration of (bumped) chips (and sensors) 
modules
• CMOS ICs (Bonn)
- very deep submicron (65 nm),
- vias first  new CMOS technologies
• 3D post processing and testing (IZM, Bonn) – ICs
and modules
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Norbert Wermes – University of Bonn – Nov 20 - 2013
Tasks and Deliverables
• Tasks:
– New optical data transmission (uWuppertal)
– Highly integrated full custom pixel moduls (uBonn)
• Vertical integration of CMOS interconnections
– Vias first
– Vias last and post processing (Fraunhofer)
• Very deep submicron technology (65 nm) pixel chips
– Interconnect structures with reduced bump and pitch sizes
(Fraunhofer)
• Deliverables:
– USBpix setup for module tests commissioned, M12 ✔
– Pixel Sensor and ASIC FE qualification modules, M18 ✔
– Full system test of module to DAQ, M36 ✔ (ahead of time)
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Norbert Wermes – University of Bonn – Nov 20 - 2013
R&D for New Data Links
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This research project focuses on the optical data transmission
between detector systems and readout electronics.
ATLAS IBL data link as the starting point
– A new optical off-detector card is to be introduced into the
system
– Studying the optical link parameters and performance for
building experience
Driving it to higher requirements for upcoming detector systems:
– more radhard optical components (laser / PIN)
– larger bandwidth
– link architecture and data protocol
– less power
– less space
Knowledge about electronics and optics will be gained, including
modern FPGA and computing techniques
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Norbert Wermes – University of Bonn – Nov 20 - 2013
Off-detector
electronics
fibres
On-detector
components
cables
Detector
Typ. data link
structure
ESR4 (Wuppertal): Detector Readout
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Rouhina Behpour started in April 2013
Until now:
– Work in IBL Back of Crate (BOC) card production test
preparation
– Main topic was to investigate the optical measurements for
the testing and to qualify the optical components (see
examples below)
– Boards will be delivered this week
– After initial testing, the boards will be integrated into IBL
surface tests and then installed and commissioned in the
Pit
Frequency
Rise time
Power
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Norbert Wermes – University of Bonn – Nov 20 - 2013
IBL BOC card
ESR4: Future Plans
•
For future detector readout systems higher
requirements need to be addressed:
– Investigate in higher bandwidth systems,
starting from IBL (160 Mb/s) in several
steps towards multi Gb/s transmission
– Test bed available: GBT Link Interface
Board (GLIB), capable of transmission up
to 5 Gb/s raw data
– Implement a test stand for optical
transmission
– Set up an IBL-electronics based readout
to test detector connection possibilities
(combine several modules into one link,
etc.)
– Test of different optical components,
further architectures (crate based, PC
based, etc.), different link styles, and
bandwidths for next generations of the
readout
GBT Link Interface Board
*GBT: GigaBit Transceiver
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Norbert Wermes – University of Bonn – Nov 20 - 2013
IC development and 3D integration
FE-I4 Chip as starting point and working horse for:
– development of a testing environment for chips and modules (USBpix)
– module building and integration
• building of qualification modules ✔ ... accomplished (in context of IBL)
• building of a serially powered full stave ✔ ... accomplished (thesis
Laura Gonella)
– full system (IBL) test to DAQ ✔ ... accomplished (in context of IBL)
– 3D integration (post processing)
• through silicon vias and post processing (with IZM) ✔ ... 1st published
• merging of FE-I4 with monolithic pixel sensors ✔ ... see talk (who?)
• monolithic pixel sensor development ✔ ... successfully submitted and
tested
– further chip development towards
• very deep submicon technologies (65 nm) ✔ ... Prototype chips done
... RD53 founded and active
• 3D CMOS integration (Tezzaron/Chartered) ✔ ... evaluated, bonding to
sensors underway
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Norbert Wermes – University of Bonn – Nov 20 - 2013
IC development and 3D integration
FE-I4 Chip as starting point and working horse for:
– development of a testing environment for chips and modules (USBpix)
– module building and integration
• building of qualification modules ✔ ... accomplished (in context of IBL)
• building of a serially powered full stave ✔ ... accomplished (thesis
Laura Gonella)
ESR2
filled
... ...
Viacheslav
Filimonov
(from
– full (Bonn):
system (IBL)
test9/2012
to DAQ ✔
accomplished
(in context of
IBL) Russia)
– 3D integration (post processing)
ESR6• (IZM):
redirected
... currently
through....
silicon
vias and to
postCERN
processing
(with IZM)being
✔ ... 1stfilled
published
• merging of FE-I4 with monolithic pixel sensors ✔ ... see talk (who?)
• monolithic pixel sensor development ✔ ... successfully submitted and
tested
– further chip development towards
• very deep submicon technologies (65 nm) ✔ ... Prototype chips done
... RD53 founded and active
• 3D CMOS integration (Tezzaron/Chartered) ✔ ... evaluated, bonding to
sensors underway
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Norbert Wermes – University of Bonn – Nov 20 - 2013
FE-I4
•
successor of current (50 x 400 µm )
FE-I3 for IBL
20.2 mm
FE-I4
2
– smaller pixels (50 x 250 µm2)
– lower noise and threshold operation
– higher data rate compatibility
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•
IBM 130 nm
array size: 80 col. x 336 rows
26880 pixels, 7x107 transistors
average hit rate @ 1%
inefficiency
= 400 MHz/cm2
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•
2.8 mm
2.0 mm
max. trigger rate: 200 kHz
FE-I4 assembly
FE-I4 works well, IBL production
successful, currently issues with
corrosion of wire bonds,
production
continues Norbert Wermes
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10.8 mm
column drain architecture
with local hit storage
FE-I3
18.8 mm
•
7.6 mm
– University of Bonn – Nov 20 - 2013
Test setup: USBpix
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Full featured test system for all kind of electrical tests of IC, modules
(single or multiple chips.
Lab tests and beam test supported
External measuring and control function can be added: environmental
chamber control, IV measurements with external source meter etc.
Data analysis framework implemented and in operation  Module Analysis
Dev. of next generation (based on USB 3.0) completed; production under way
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Norbert Wermes – University of Bonn – Nov 20 - 2013
65 nm chip ... comparison to FE-I4
400µm
ATLAS Pixel FE chips
FE-I4
FE-??
FE-I3
65 nm
~2 × 2 cm2
The smallest
transistor in
HEP !!
~0.6 × 1.1 cm2
250 nm technology
130 nm technology
65 nm technology
pixel size 400 × 50
µm2
pixel size 250 × 50
µm2
pixel size 125 × 25
µm2
3.5 mil. transistors
80 mil. transistors
~ 500 mil. transistors
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Norbert Wermes – University of Bonn – Nov 20 - 2013
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First prototypes in 65nm (Bonn and LBNL)
FE-T65-1,to test analog perf.
CSA + Discr. versions
M. Havranek, Bonn
Analog FE array proto
A. Makkaoui, LBNL
400mV
1.6 GHz PLL-PRBS-CML
T. Kishishita, Bonn
unloaded-ENC ~ 80eRMS jitter ~ 60ps
CSA with continuous reset
1.6 Gbps, PRBS, preamp on
dyn. comp.: 2.4μW
@40MHz
other Bonn prototypes: SAR-ADC, LVDS
a problem still to understand/solve: pMOS transistors don’t stand more than 400 Mrad (CPPM)
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Norbert Wermes – University of Bonn – Nov 20 - 2013
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RD53 ... 65 nm R&D Collaboration
R&D collaboration to promote/share common IBM 65 nm pixel chip design blocks
Institutes from ATLAS: CERN, Bonn, CPPM, LBNL, LPNHE Paris, NIKHEF,
(also CMS, ALICE)
New Mexico, RAL, UC Santa Cruz
Spokespersons:
Work Packages
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Jorgen Christiansen (CERN)
Maurice Garcia-Sciveres (LBNL)
WG1 Radiation
WG2 Top level design
WG3 Simulation test bench (coord. Hemperek,
Bonn)
WG4 IO pad library
WG5 Analog design
WG6 IP blocks (coord. H. Krüger ? tbc)
Norbert Wermes – University of Bonn – Nov 20 - 2013
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3D integration
vias LAST, post-processing
Super
Contact
vias FIRST, CMOS circuits
Tezzaron – Chartered, 130 nm
50 μm
M1
M2
M3
M4
M5
M5
M4
M3
M2
M1
250 μm
Super
Contact
FE-I4 CMOS 130 nm
IZM Berlin
CPPM-Bonn• after a long
50 μm
tapered TSV
125 μm
FE-I3
operated
from backside
FE-TC4 CMOS 130 nm 2 layers
•
struggle analog
+ digital parts
work together
now: bond sensor
Bonn
Am-241 scan
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M
6M
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Norbert Wermes – University of Bonn – Nov 20 - 2013
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3D integration R&D
vias LAST, post-processing
Super
Contact
vias FIRST, CMOS circuits
Tezzaron – Chartered, 130 nm
50 μm
M1
M2
M3
M4
M5
M5
M4
M3
M2
M1
250 μm
Super
Contact
FE-I4 CMOS 130 nm
IZM Berlin
CPPM-Bonn• after a long
50 μm
tapered TSV
125 μm
FE-I3
operated
from backside
FE-TC4 CMOS 130 nm 2 layers
•
struggle analog
+ digital parts
work together
now: bond sensor
Bonn
Am-241 scan
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M
6M
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Norbert Wermes – University of Bonn – Nov 20 - 2013
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3D integration R&D
vias LAST, post-processing
Super
Contact
vias FIRST, CMOS circuits
Tezzaron – Chartered, 130 nm
50 μm
M1
M2
M3
M4
M5
M5
M4
M3
M2
M1
250 μm
Super
Contact
FE-I4 CMOS 130 nm
IZM Berlin
CPPM-Bonn• after a long
50 μm
tapered TSV
125 μm
FE-I3
operated
from backside
FE-TC4 CMOS 130 nm 2 layers
•
struggle analog
+ digital parts
work together
now: bond sensor
Bonn
Am-241 scan
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M
6M
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Norbert Wermes – University of Bonn – Nov 20 - 2013
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Advanced interconnects
Further development of interconnect
structures to reduce the bump size and the
pitch for further detector generations
25µm bumps / 55µm pitch
10µm pillars / 20µm pitch
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Tasks:
• design of small size interconnection structures
• Investigation of material requirements
• Process development and prototyping
• Development of modified assembly technologies for
small size interconnection structures
• Reliability investigation
Norbert Wermes – University of Bonn – Nov 20 - 2013
Talent
Monolithic CMOS Pixels
... sensor and chip  one monolithic unity (= dream for a long time)
... CMOS imagers don’t have 100% fill factor  needed for HEP
... conventional MAPS (on epitaxial Si) not suited for LHC
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Norbert Wermes – University of Bonn – Nov 20 - 2013
HVCMOS
FE-Chip (FE-Ix)
I. Peric et al.
 uses AMS 180 nm HV process (p-bulk) ... 60-100 V
 deep n-well to put pMOS and nMOS (in extra p-well)
 some CMOS circuitry possible (ampl. + discr.)
 need / profit from FEI4 and followers
 ~10-20 µm depletion depth  1-2 ke signal
 various pixel sizes (~20x20 – 50x125 µm2)
 several prototypes
 also strip like geometries possible
 replaces „sensor“ (amplified signal)
in hybrid pixel bump bonding or
glue bonding
 indications of radiation hardness to
~ 1016 neq / cm2
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HV2FEI4-V2
w/ radhard design features
Norbert Wermes – University of Bonn – Nov 20 - 2013
Sr-90, 1400 e-
Fe-55, 1660 e-
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HVCMOS
preliminary irradiation tests: using reactor neutrons 1x1015 and 1x1016 neq/cm2
also to protons and X-ray (862 Mrad !)
DESY testbeam
HV2FEI4 glue bonded to FEI4
and irradiated to 1 x 1015 neq/cm2
still working
very preliminary results after
1 x 1016 neq/cm2
- @RT after ~30 days / annealing
- source scan with ~25 V bias
- still alive, noise occ ~10-10
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Norbert Wermes – University of Bonn – Nov 20 - 2013
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fully depleted DMAPS
 Bonn approach: address different vendors for process options
 150nm – submitted Q4 2012
 full CMOS
 n-type > 2kOhm-cm substrate
 thinned
 back implanted
 180nm – submitted Q1 2013
 full CMOS
 p-type > 1kOhm-cm substrate
 full wafers -> thinning/back implanting possible
 180nm - submitted Q1 2013
addn’l backside contact & high resistivity
-> 50 – 100 µm depletion and full CMOS
 full CMOS
 p-type - initially 100 Ohm-cm
 very HV isolation guaranteed (SOI)
 130nm – submission Q4 2013
 HV-CMOS / full CMOS
 p-type >3kOhm-cm
 full wafers -> thinning/back implanting possible
 150nm – submission Q4 2013
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 HV-CMOS(CCPD) /full CMOS / possibly T3
 p-type >2kOhm-cm (~4-5k Ohm-cm)
 thinned
 back implanted
 full wafers
sideward drift to small collection diode
full CMOS full depletion
Norbert Wermes – University of Bonn – Nov 20 - 2013
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DMAPS (prototype results)
collecting
charge eff.
from entire
pixel area
still to be
proven
EPCB01
352 pixels
40×40 µm2
M. Havranek
T. Hemperek
50µm, back side processed, full CMOS, fully depleted (>2kOhm-cm
substrate)
good
Fe-55
noise (~30 e)
and
thres. disp. (~80 e)
full depletion
gain variation ~10%
full depletion
from cluster size
saturation
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Norbert Wermes – University of Bonn – Nov 20 - 2013
Sr-90
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Conclusions
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•
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2 ESR-positions successfully filled
ESR6 currintly being filled
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network working as planned
•
most WP3 tasks already met
ahead of schedule
Norbert Wermes – University of Bonn – Nov 20 - 2013