Transcript Test Setups for the FE-I4

Test Setups for the FE-I4
Integrated Circuit
Stewart Koppell
8/1/2010
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Test Hardware – USBPix System
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Hardware – USBPix System
The USBPix System has 3 main components:
1. Main Board: Contains SRAM, FPGA, microcontroller. Responsible for
translating commands into signals to be sent to IC and interpreting/parsing
the output. Communicates with a computer via USB cable
Emulator
(bottom)
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1
2. Single Chip Adapter
Card: Extension of
the Main board that
can be exchanged to
allow the system to
interface with
multiple FE-I4s. The
Adapter Card also
translates the
outgoing signal into
LVDS.
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Hardware – USBPix System
3. Add-on Card: Mount for the emulator/FE-I4. It
connects to the Adapter Card via type-0 Cable
An alternative setup replaces the Type-0 Cable
and Add-on Card with:
• Pin card: Connects to Adapter Card with a flat
ribbon cable. Allows data input/output and clock
signals to be accessed from pins.
• Carrier Board: Connects to the Pin card by
jumper wires. Mount for emulator/FE-I4.
Emulator
(bottom)
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Emulator
While the FE-I4 is being fabricated, debugging of the testing hardware and
software will be done using a stand-in emulator. The central component of
the emulator is an FPGA, which was configured using VHDL.
emulator versions:
•Version 0: sends out a constant
stream of words (i.e. 0x abc123,
0x efg789). In the USBPix system
they are parsed and stored in the
SRAM where they can be retrieved
by the testing software.
•Version 1: implements a few 16 bit
configuration registers
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Commands
• Level 1 trigger: 11101
• Calibration pulse: 10110 0100
• Write Register:
Slow Command
Header
WrReg
Chip ID
Register
Address
Register Data
10110 1000 0010 1000 00010 1111111111111111
• Write Front End:
10110 1000 0100 0000 000000 1111111111111111
1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111
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Test Software
Arbitrary Bit Stream Generator (ABSG)
The ABSG allows a
user to generate bit
streams representing
standard commands
by pressing buttons.
Once a bit stream is
generated, it can be
edited by hand
before being sent out
through the USBPix
hardware.
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Software: Arbitrary Bit Stream Generator (ABSG)
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Software: Arbitrary Bit Stream Generator (ABSG)
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Software: Arbitrary Bit Stream Generator (ABSG)
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Software: Arbitrary Bit Stream Generator (ABSG)
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Software: Arbitrary Bit Stream Generator (ABSG)
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Test Software: Pixel Manager
•The Pixel Manager provides a
visual representation of the FE-I4
which can be used to activate and
deactivate arbitrary regions of
pixels.
•One double column at a time is
shown (center left), with buttons
which control the activation state of
groups of 21 pixels.
•The adjacent View buttons display
the pixels in the corresponding
rows (center left) which can be
individually activated or
deactivated.
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Test Software: Pixel Manager
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Test Software: Pixel Manager
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Test Software: Pixel Manager
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Test Software: Pixel Manager
•FE pixel = 2 x 10 pixels on screen.
•Dark Grey=off
•Light Grey=on
•Green=hit (darker=stronger)
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Parser
3 types of files:
Configuration
#config
PrmpVbp_r
Vthin
DisVbn_CPPM
PrmpVbp
TdacVbp
DisVbn
Amp2Vbn
Amp2VbpFol
PrmpVbp_T
Amp2Vbp
FdacVbn
Amp2Vbpff
PrmpVbnFol
PrmpVbp_L
PrmpVbpf
PrmpVbnLcc
Spare1
PixelStrobes
S0
S1
LvdsIref
BonnDac
PllIbias
LvdsDrvVos
TempSensBias
PllIcp
DAC8SPARE1
PlsrIdacRamp
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5
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10
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14
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16
17
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19
20
21
22
23
24
25
26
27
28
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
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13
13
14
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16
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17
17
0xFF00
0x00FF
0xFF00
0x00FF
0xFF00
0x00FF
0xFF00
0x00FF
0xFF00
0x00FF
0xFF00
0x00FF
0xFF00
0x00FF
0xFF00
0x00FF
0x0001
0x3FFE
0x4000
0x8000
0xFF00
0x00FF
0xFF00
0x00FF
0xFF00
0x00FF
0xFF00
0xFF00
Task
50
64
64
32
0
128
69
26
66
64
66
175
64
66
16
0
0
16380
0
1
0
0
0
0
0
0
0
0
#taskdefine
task1
comm,wrRegister,vthin,24
comm,rdRegister,tdacvbp
comm,rdRegister,vthin
endtask
task2
comm,rdRegister,tdacvbp
comm,wrRegister,tdacvbp,100
comm,rdRegister,tdacvbp
endtask
Command
#command
comm,wrRegister,vthin,17
comm,rdRegister,tdacvbp
task,task1
comm,rdRegister,disvbn
loop,5,task,task2
loop,5,comm,wrRegister,vthin,10
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Parser
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Test Hardware – SLAC system
The other used hardware setup. It uses an Ethernet DHCP server connection
rather than a USB cable to connect to the computer. The RCE and Controller
(comparable in function to the USBPix main board) are
housed in a two-slot
ATCA electronics crate.
The HSIO (comperable
in function to the Single
Chip Adapter Card) is
connected to the ATCA
crate with optical fiber
and communicates
directly with the
emulator/FE-I4.
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Conclusions
The ABSG and Pixel manager extend the functionality of the USBPix
software by allowing more convenient ways of testing and configuring
the FE-I4
The ABSG allows:
• testing of chip response to single Event Upsets (SEU) by
manually flipping bits before sending a command
• testing of chip response to various ways of ordering and timing
of commands
The Pixel Manager allows:
• arbitrary regions of pixels on the chip to be activated/deactivated
for testing
• generation of a colored map of the chip representing the
activation state of pixels and the locations/strengths of hits
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