Transcript RISC

RISC
by
Betty Tang
What is RISC?
RISC stands for Reduced Instruction Set
Computer.
It is a computer CPU design philosophy
that favors a smaller and simpler set of
instructions that all take about the same
amount of time to execute .
Also referred to as load-store architectures.
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What inspired RISC?
The idea was inspired by:
• The discovery that many features that were
included in traditional CPU designs for speed
were being ignored by the programs that were
running on them.
• The disparity of speed of the CPU in
relation to memory speed.
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Pre-RISC design Philosophy
(CISC)
• Compiler technology did not exist!
• Computer architects created more and more
complex instructions which were direct
representation of high level programming
languages.
• At the time, hardware design was easier than
compiler design, so the complexity went into
hardware.
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CISC Characteristics
• Instruction packing
– Memories were small and precious.
• In 1979, a 32KB memory cost $329. In 2004, 512MB
cost $75.
• An order of 4 magnitude decrease in $ per byte!
– Therefore, it was advantageous to pack as much
information in a single instruction as possible to
avoid access slower resource.
– As a result, instruction are highly encoded, variable
sized, can perform multiple operations and did both
data movement and data calculation.
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CISC Characteristics
• x86 example:
.date
var1 DWORD 30000h
.code
add var1, 40000h
calculation
data storage data movement
– In a single instruction, a source operand is added to a
destination operand, and the sum is stored in the
destination.
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CISC Characteristics (cont’d)
• Small set of registers
– CPU only had a few registers due to the limitation in
silicon integration and available RAM.
– Silicon integration was not mature enough to free up
space in the chip area or board area for a larger
register sets.
– Having a large number of registers would have
required a large number of instruction bit using
precious RAM.
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CISC Characteristics (cont’d)
• “Orthogonal” addressing mode
– The general goal was to provide every
possible addressing mode for every
instruction.
– This led to CPU complexity but in theory
every command could be tuned, making the
design faster than if simpler command is
used.
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The emerging reasons for RISC
• In the late 1970s, research showed the majority of
these “orthogonal” addressing modes were ignored by
most programs.
– A side effect of the increasing use of compilers to generate
the programs, as opposed to writing them in assembly
language. The compilers in use at the time did not take
advantage of the feature provided by CISC CPUs.
• Another discovery was that since orthogonal mode were
rarely used, complex instruction tended to be slower
than a number of smaller operations doing the same
thing.
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The emerging reasons for
RISC (cont’d)
• CPU starts to run ever faster than
memory and the trend continue.
• It become apparent that more registers
would be need to support these higher
operating frequencies.
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RISC design philosophy
• New ideas about how to dramatically increase
performance of the CPUs were starting to develop in
the early 1980s, namely, pipelining and parallel
processing.
• Pipelining: include a pipeline which would break down
instructions into steps, and work on one step of
several instructions at the same time.
• Parallel processing: instead of working on one
instruction, processors would look at the next
instruction in the pipeline and attempt to run it at the
same time.
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RISC design
philosophy(cont’d)
• Pipelining and Parallel processing relied on increasing
speed by adding complexity to the basic layout of the
CPU, as opposed to the instructions running on them.
• In order to include these feature, something would have
to be removed to make room.
• RISC was design to incorporate these two technique
since the core logic of a RISC CPU was much simpler
than in CISC designs.
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RISC design
philosophy(cont’d)
• By the late 1980s, RISC were significantly outperforming
their CISC counterparts.
Four stages in executing an instruction in CISC:
– Fetch, decode, execute, write
– Each instruction will take at least 4 clock cycles, some complex
instructions can take even more
These same stages exist in a RISC machine, but the stages are
execute in parallel. As soon as one stage completes, it passes on
the result to the next stage and then begins working on another
instruction. This grantees each instruction will take only one
clock cycle.
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RISC Characteristics
•
Fewer transistors dedicated to the core logic.
•
Larger register set
– 32 general purpose registers in MIPS vs. 16 in Intel’s x86
•
Simple instruction set
– the instruction set contains simple, basic instruction from which more
complex instructions can be composed.
•
Single machine-cycle instructions
– most instructions complete in one machine cycle, which allows the
processor to handle several instructions at the same time via pipelining.
•
Uniform instruction encoding which allows faster decoding
•
Complete separation between instructions that compute and
instructions that access memory
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RISC Characteristics (con’t)
•
Complete separation between instructions that compute and
instructions that access memory
•
MIPS example to add 3000h to memory:
.data
.globl var
var:
.word 500h
__start:
lw
$t0, var
addi
$t1, $t0, 3000h
sw
var, $t1
.end
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RISC Machine
•
The first system was designed in 1964 by Jim Thornton and Seymour
Cray as a number-crunching CPU.
•
Another load/store machine was Data General Nova minicomputer,
designed in 1968.
•
Yet, most public RISC designs were the results of university research
programs.
•
In 1980, under the direction of David Patterson, UC Berkeley's RISC
project aimed to gain performance through the use of pipelining and
an aggressive use of register windows.
•
CPU with register windows has 128 registers, but programs can only
use 8 of them at a time. This limit per procedure results in very fast
procedure calls.
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RISC Machine(cont’d)
• In 1981, John Hennessy started a similar project called MIPS
at Stanford University. MIPS focussed almost entirely on the
pipeline, making sure it could run as “full” as possible.
• A number of successful RISC platforms and architectures were
developed in the 80’s to early 90’s.
– MIPS: found in most SGI computers, PlayStation and Nintendo 64 game
consoles.
– IBM’s Power series: used in all their minis and mainframes
– Motorola and IBM’s PowerPC: used in all Apple Macintosh computers
– Sun’s SPARC and UltraSPARC
– HP’s PA-RISC HP/PA
– DEC Alpha
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MIPS Instruction Encoding
Register-Register
31
26 25
Op
21 20
Rs1
16 15
Rs2
11 10
6 5
Shamt
Rd
0
Opx
Register-Immediate
31
26 25
Op
21 20
Rs1
16 15
0
immediate
Rd
Branch
31
26 25
Op
Rs1
21 20
16 15
Rs2/Opx
0
immediate
Jump / Call
31
26 25
Op
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target
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x86 Instruction Encoding
5
3
PUSH Reg
6
2
8
8
D/w
postbyte
Disp.
2
8
8
4
4
V/w
postbyte
Disp.
JE
Cond
7
1
8
8
TEST
W
postbyte
Immediate
MOV
6
SHL
4
3
1
ADD Reg W
8
16
16
CALLF
Offset
Segment Number
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8
Disp.
8
Disp.
Decline of RISC, is it really?
• Despite many successes, RISC has not make it into the
desktop PC and commodity server markets.
• Intel’s x86 still remains the dominant processor architecture.
– x86 had a very large base of proprietary applications. It is
very difficult for companies to switch to RISC.
– Intel had spend large amounts of money on processor
development.
– Recall that RISC is a set of design philosophies and
practices instead of an architecture. Instead of allowing
itself to lag behind in the competitive market, Intel started
to apply many of RISC principles to their CISC processors.
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Modern CPU designs
•
The difference between CISC and RISC today is only in their
instruction sets (ISA).
•
Important development in the 90s encourage separations between
CPU architecture designs from instruction designs. Most CPU today
will have a translator to translate native instruction set to internal
instruction set.
•
Recall the traditional design of CISC favors instruction packing?
Nowadays, CISC machine takes CISC instructions and translate them
into simpler RISC-like instructions.
•
In addition, modern CISC design have include large number of
pipelines, utilize techniques such as instruction reordering, branch
prediction (continuous improvement in compiler designs to inject
hints to CPU what to expect next), Simultaneous Multithreading
(SMT) to increase CPU performance.
•
Pipelining and branch prediction were all inherently RISC and
continue to play an important part in modern CPU designs.
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Further reading
CISC vs RISC
http://ctas.east.asu.edu/bgannod/CET520/Spring02/Projects/demone.htm
Simultaneous Multithreading
http://en.wikipedia.org/wiki/Simultaneous_multithreading
Computer Organization & Design: The Hardware/Software Interface
Patternson, David. A and Hennessy, John L.
ISBN: 1558606041
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