Transcript Memory - Cache

Chun Chiu
Overview
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What is RISC?
Characteristics of RISC
What is CISC?
Why using RISC?
RISC Vs. CISC
RISC Pipelines
Advantage of RISC / disadvantage of RISC
Advantage of CISC / disadvantage of CISC
Example of CISC/RISC
Combine RISC and CISC
History
What is RISC?
• RISC is the abbreviation of “Reduced
Instruction Set Architecture”.
• Reduced Instruction Set Architecture is a type
of microprocessor that recognizes a relatively
limited number of instructions.
Characteristics of RISC
• One instruction per cycle
– Instruction length, addressing mode, the formats are
uniform: this can make full use of pipelining.
• Register-to-register operations
– Only load and store instructions access memory.
• Simple addressing modes
– Almost all instructions use simple register addressing.
Other, more complex modes can be synthesized in
software from simple ones.
• Simple instruction formats
– It uses same length instructions so that the instructions are
aligned on word boundaries and may be fetched in a single
operation.
RISC Pipelines
A RISC processor pipeline operates in much the same way, although
the stages in the pipeline are different. While different processors
have different numbers of steps, they are basically variations of these
five, used in the MIPS R3000 processor:
- fetch instructions from memory
- read registers and decode the instruction
- execute the instruction or calculate an address
- access an operand in data memory
- write the result into a register
Basic five-stage pipeline in a RISC machine:
IF = Instruction Fetch
ID = Instruction Decode
EX = Execute
MEM = Memory access
WB = Register write back
In the fourth clock cycle (the green column), the earliest instruction
is in MEM stage, and the latest instruction has not yet entered the
pipeline.
And what is CISC?
• CISC is the abbreviation of “Complex
Instruction Set Computer (or computing)”
• It is a type of microprocessor design.
The CISC architecture contains a large set of
computer instructions that range from very
simple to very complex and specialized. Which
was Invented earlier than RISC.
Why using RISC?
Traditional CISC structure has inherent
shortcomings, the development of computer
technology is constantly introducing new and
complex set of instructions.
To support these new instructions, the computer
will be more complex architecture, however, in many
instructions of CISC’s instruction set, almost 20%
instructions will be use repeatedly, and it accounted
for 80% of the entire code. The remaining 80% of the
instruction is not frequently used in the
programming, but it still take 20% of the rest code.
Obviously, this structure is not reasonable.
Based on the above irrationality, 1979, University
of California at Berkeley in the United States put
forward the concept of RISC, RISC is not simply to
reduce the instruction, but to focus on how to make
computers simple and reasonable way to improve
operations Speed​​.
RISC structure of the highest priority to select the
simple instructions frequently used to avoid complex
instructions; to fixed instruction length, to reduce
instruction format and the ways to search.
Based on control logic, do not use or use less
amount of microcode to achieve above purpose.
RISC Vs. CISC
• The RISC machine executes instructions faster
because it does not have to go through a
microcode conversion layer.
• The RISC compiler generates more instructions
than the CISC compiler for the same
processing.
CISC
Emphasis on hardware
Includes multi-clock
complex instructions
Memory-to-memory:
"LOAD" and "STORE"
incorporated in instructions
Small code sizes,
high cycles per second
Transistors used for storing
complex instructions
RISC
Emphasis on software
Single-clock,
reduced instruction only
Register to register:
"LOAD" and "STORE"
are independent instructions
Low cycles per second,
large code sizes
Spends more transistors
on memory registers
• The way RISC call subroutine is different with
CISC:
– CISC need to keep the context in stack and also
operate in memory, When it call or return a
function.
– RISC do it in different way, RISC keep them in
register, and it also pass parameters by register.
– RISC interrupt subroutine can be regarded as a
special link.
– When CISC interrupt subroutine, will be push all
the data in the register to stack.
Advantage of RISC
1. RISC is that they can execute their instructions very
fast because the instructions are so simple. The
instructions usually finish in 4 or 5 processor cycle.
2. Because instruction operand has to store in the
register, thus the operation time is unified.
3. RISC are used pipelining, cache memory, less or do
not use microcode.
4. More important advantage is that RISC chips require
fewer transistors, which makes them cheaper to
design and produce.
Disadvantage of RISC
• RISC architectures put a greater burden on the
software.
– Is this worth the trouble because conventional
microprocessors are becoming increasingly fast
and cheap anyway?
Example of CISC/RISC
• The PowerPC microprocessor(old Mac) , used in
IBM's RISC System/6000 workstation and
Macintosh computers, is a RISC microprocessor.
• Intel's Pentium microprocessors are CISC
microprocessors.
Combine RISC and CISC
• RISC takes each of the longer, more complex
instructions from a CISC design and reduces it
to multiple instructions that are shorter and
faster to process.
LLH
•Java
•C
•Python
•Scheme
•Prolog
•C++
•C#
•Java script
•Lisp
•Ruby
History
• The original RISC prototype computer, called the 801 Minicomputer, was
built at IBM's Research Division in 1980 -- the result of a project that
began in the 1970's.
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1950s IBM instituted a research program
1964 Release of System/360
Mid-1970s improved measurement tools demonstrated on CISC
1975 801 project initiated at IBM’s Watson Research Center
1979 32-bit RISC microprocessor (801) developed led by Joel Birnbaum
1984 MIPS developed at Stanford, as well as projects done at Berkeley
1988 RISC processors had taken over high-end of the workstation market
Early 1990s IBM’s POWER (Performance Optimization With Enhanced RISC)
architecture introduced with the RISC System/6k
– AIM (Apple, IBM, Motorola) alliance formed, resulting in PowerPC
References
Internet sources:
- http:// www.computerhistory.org/collections/accession/102657026
- http://www.karbosguide.com/books/pcarchitecture/chapter12.htm
- http://en.wikipedia.org/wiki/Instruction_pipeline
- http://www.webopedia.com/TERM/R/RISC.html
Book sources:
- Computer Organization And Architecture, 8th Edition.