Transcript UNIT 5 PPT

Chapter – V
Memories
ROM
• A combinational circuit with n inputs(Address inputs A0,A1,…,An-1),
b outputs(data outputs D0,D1,…,Db-1).
• Neglecting propagation delays, a ROM’s data outputs at all times
equal the output bits in the truth table selected by the address
inputs.
• ROM is a non-volatile memory i.e., its contents are preserved even
if power is off.
ROM’s for Combinational logic functions
Internal ROM Structure
Sneak Paths
• The ROM has to use diodes, not the direct connections at each location
where a 1 is to be stored.
• If a few diodes such as the ones in row 3 are replaced by direct
connections, if address inputs are 101, then ROW5_L is asserted, and only
D1_L is supposed to be pulled LOW to create an output of 0010.
• But the direct connections allow current to flow along sneak paths, so that
bit lines D2_L and D0_L are also pulled LOW and the incorrect output is
obtained as 0111.
• Remedy : Use diodes so that sneak paths are blocked by reverse-biased
diodes, and correct results are obtained.
Transistors as ROM Elements
• MOS ROMs use a transistor instead of a diode at each location where a bit is
to be stored.
• The row decoder has active high outputs.
• When a row line is asserted, the NMOS transistors in that row are turned on,
which pulls the corresponding bit lines low.
PROMs
• PROMs are usually EPROMs housed in inexpensive packages without quartz lids, called as
one-time programmable (OTP) ROMs.
• EEPROM-electrically erasable PROM.
• The floating gates in an EEPROM are surrounded by a much thinner insulating layer and can
be erased by applying a voltage of the opposite polarity as the charging voltage to the nonfloating gate.
• Large EEPROMs (1MBit or larger) allow erasing only in fixed-size blocks, typically 128-512
Kbits (16-64 Kbytes) at a time, called as flash EPROMs or flash memories, as erasing occurs in
a flash.
• programming or "writing" an EEPROM location takes much longer than reading it, so an
EEPROM is no substitute for the read/write memories .
• As the insulating layer is so thin, it can be worn out by repeated programming operations.
• Hence EEPROMs can be reprogrammed only a limited number of times, as few 110,000 times
per location.
• EEPROM s are typically used for storing data that must be preserved when the equipment is
not powered.
EPROMs
• Operate at +5V, VPP is used to apply the programming voltage.
• Larger ROMs have wider data outputs of 16 or 32 bits. Eg:
AMD29LV640 flash memory with 64Mbits in 256 32-Kbyte sectors.
• Much smaller PROMs are also produced with a 3-bit serial
interfaces for specialized applications, such as downloading the
programming information into FPGAs.
• Multiple flash memories are often packaged into a single credit card
size module for applications requiring large amounts of non-volatile
storage. Eg: in digital cameras, where a single high resolution image
may require as much as 4Mbytes.
• In 1999, the largest card flash card was sold by industry leader
SanDisk Corporation and contained 192 Mbytes (1536 Mbits) of
memory.
ROM Control Inputs and Timing
ROM Applications
• For program storage in microprocessor systems.
• To provide a low-cost realization of a complex or "random"
combinational logic function.
• μ-law coded voice signals
• In digital telephony as a digital conference circuit.
• In the analog telephone network, it's fairly easy to make a conference
connection between three or more parties. Just connect the analog
phone wires together and you get an analog summing junction, so each
person hears everyone else.
• In the digital network, of course, chaos would result from just shorting
together digital output signals. Instead, a digital conference circuit must
include a digital adder that produces output samples corresponding to
sums of the input samples.
Advantages of building complex combinational functions
with ROMs
• Ease and speed of design.
• For a moderately complex function, a ROM-based circuit is usually faster than a
circuit using multiple SSI/MSI devices and PLDs, and often faster than an FPGA or
custom LSI chip in a comparable technology.
• The program that generates the ROM contents can easily be structured to handle
unusual or undefined cases that would require additional hardware in any other
design.
• A ROM's function is easily modified just by changing the stored pattern, usually
without changing any external connections.
Eg., the PCM attenuator and adder ROMs in this subsection can be changed to use
8-bit A-law PCM, the standard digital voice coding in Europe.
• The prices of ROMs and other structured logic devices are always dropping,
making them more economical, and their densities are always increasing,
expanding the scope of problems that can be solved with a single chip.
Disadvantages of ROM based Circuits
• For simple to moderately complex functions, a ROM based
circuit may cost more, consume more power, or run slower
than a circuit using a few SSI/MSI devices and PLDs or a small
FPGA.
• For functions with more than 20 inputs, a ROM based circuit is
impractical because of the limit on ROM sizes that are
available.
• Eg: to build a 16-bit adder in ROM – it requires billions of bits.
Dynamic RAM
DRAM
• The basic memory cell in an SRAM, a D latch, requires four gates in a discrete design, and
four to six transistors in a custom-designed SRAM LSI chip.
• In order to build RAMs with higher density (more bits per chip), chip designers invented
memory cells that use as little as one transistor per bit.
Internal Structure of a 64Kx1 DRAM
Dynamic-RAM Timing
• There are many different timing scenarios for different DRAM types and
operations.
• The most common cycles for conventional DRAM that relates it to the
internal structure of the device.
• The most striking aspect of conventional DRAM timing is that there is no
clock.
• Instead, DRAM operations are initiated and completed on both the rising
and falling edges of RAS_L and CAS_L.
DRAM Timing
• The timing for a RAS-only refresh cycle is shown in Figure 10-34. This cycle is used to refresh a row of
memory without actually reading or writing any data at the external pins of the DRAM chip.
• The cycle begins when a row address is applied to the multiplexed address inputs (eight bits in the case of
a 64K x I DRAM) and RAS_L is asserted.
• The DRAM stores the row address in an internal row-address register on the falling edge of RAS_L and
reads the selected row of the memory array into an on-chip row latch.
• When RAS_L is negated, the contents of the row are written back from the row latch.
• To refresh an entire 64K x 1 DRAM, the system designer must ensure that 256 such cycles, using all 256
possible row addresses, are executed every four milliseconds.
• An external 8-bit counter may be used to generate the row addresses, and a timer is used to initiate a
refresh cycle once every 15.6 μs.
DRAM Timing
• A read cycle, shown in Figure 10-35, begins like a refresh cycle, where a selected row is read into the row
latch. Next, a column address is applied to the multiplexed address inputs and is stored in an on-chip
column-address register on the falling edge of CAS_L.
• The column address is used to select one bit of the just-read row, which is made available on the DRAM's
DOUT pin.
• A three-state pin, DOUT is output enabled as long as CAS_L is asserted. In the meantime, the entire row is
written back into the array as soon as RAS_L is negated.
• Similarly, a page-mode write cycle allows multiple bits of a row to be written with a
single RAS_L and multiple CAS_L cycles.
• Two other multiple-access modes, static-column mode and nibble mode, were provided
at one time in certain DRAM chips, but these became obsolete with the marketplace
dominance of so-called extended-data-out ( EDO) DRAMs.
• In these devices, CAS_L no longer controls the output enable during read cycles;
instead, a separate OE_L control input is provided. This is important for high speed
page-mode read cycles, as it provides valid output data for a longer period of time.
Instead of turning off between successive CAS_L pulses, the output is left on
continuously (as controlled by OE_L), and page-mode read data is valid from the
beginning of one CAS_L pulse to the beginning of the next.
Synchronous DRAMs
• At each clock tick, an SDRAM's control signals RAS_L. CAS_L, and WE_L are interpreted as a
"command word," as opposed to having individual significance.
• At the same time, the high-order address bits are interpreted as a "bank select" to indicate which
bank a command applies to.
• Eg., an intelligent SDRAM controller can use four ticks to initiate read operations in four different
banks, and then come back and read the results one per clock tick as they complete.
• Internal timing in an SDRAM is derived from the clock input CLK.
• Typically, a RAS signal to the internal array will be asserted immediately after 1 the clock tick when
a read or write command is given.
• To meet internal timing requirements, the chip generates an internal CAS signal at a later clock tick.
How many ticks later is a function of the CLK frequency and the speed grade of the SDRAM chip
itself.
• To accommodate differing requirements, the RAS-to-CAS delay, called the CAS latency, is
programmable. This and several other important operating parameters must be downloaded into
an SDRAM at initialization. Downloading is fairly easy; the "load parameters" command is
recognized when RAS_L, CAS_L, and WE_L control signals are all asserted simultaneously, and the
parameters themselves are transferred on the address lines.
Static RAM
Read/Write Memory
• The read/write memory (RWM) consists of memory arrays in which we can store and retrieve
information at any time. Most of the RWMs used in digital systems are random-access
memories (RAMs), which means that the time it takes to read or write a bit of memory is
independent of the bit's location in the RAM.
• In a static RAM (SRAM) ("S-ram"), once a word is written at a location, it remains stored as
long as power is applied to the chip, unless the same location is written again.
• In a dynamic RAM (DRAM) ("D-ram"), the data stored at each location must be refreshed
periodically by reading it and then writing it back again, or else it disappears.
• volatile memory -Most RAMs lose their memory when power is removed.
• nonvolatile memor- Some RAMs retain their memory even when power is removed.
• Eg.: old-style magnetic core memories and modern CMOS static memories in an extralarge package that includes a lithium battery with a 10-year lifetime.
• Recently, nonvolatile ferroelectric RAMs have been introduced; these devices combine
magnetic and electronic elements on a single IC chip that retains its state even when
power is not applied, just like the old-style core memories.
Static RAM Inputs and Outputs
• A RAM has address inputs, control inputs, data inputs and data outputs.
SRAM
• The control inputs are comparable to those of a ROM, with the addition of a writeenable (WE) input.
• When WE is asserted, the data inputs are written into the selected memory location.
• The memory locations in a static RAM behave like D latches, rather than edgetriggered D Flip-Flops.
• i.e, when WE is asserted, the latches for the selected memory location are open or transparent and input
data flows into and through the latch. The actual value stored is whatever is present when the latch
closes.
• SRAM has two defined access operations:
1. Read- An address is placed on the address inputs while CS and OE are asserted. The latch outputs for
the selected memory location are delivered to DOUT.
2. Write-An address is placed on the address inputs and a data word is placed on DIN, then CS and WE are
asserted. The latches in the selected memory location open, and the input word is stored.
• While accessing SRAM, care is to taken as it can inadvertently clobber one or more
locations while writing to a selected one, if the SRAM timings are not met.
Static-RAM Internal Structure
• Each bit of memory (or SRAM cell) in a static RAM has the same
functional behavior.
• The storage device in each cell is a D latch. When a cell's SEL_L
input is asserted, the stored data is placed on the cell's output,
which is connected to a bit line.
• When both SEL_L and WR_L are asserted, the latch is open and a
new data bit is stored.
Static RAM
• A large SRAM does not contain a physical array whose dimensions equal
the logical dimensions of the memory.
• As in a ROM, the SRAM cells are laid out in an almost square array, and an
entire row is read internally during read operations.
• Eg., the layout of a 32K x 8 SRAM chip might be very similar to that of a
32K x 8 ROM.
• During read operations, column multiplexers pass the required data bits to
the output data bus, as specified by a subset of the address bits (A5—A0
in the ROM ).
• For write operations, the write-enable circuitry is designed so that only
one column in each subarray is enabled, as determined by the same
subset of the address bits.