Transcript DATE Conference Template

SuperRange: Wide Operational Range
Power Delivery Design for both STV and
NTV Computing
Xin He,
Guihai Yan, Yinhe Han, Xiaowei Li
Institute of Computing Technology, Chinese
Academy of Sciences
The need of wide operation range
• Microprocessor’s supply voltage range has been
gradually increasing in these year
– Intel Pentium Processor has a supply voltage range
from 0.9V to 1.5V to support DVFS
– Intel Sandy Bridge Processor requires a higher than
nominal voltage to boost performance
Intel Pentium Processor
0.9V
1.5V
(66.7%)
Turbo Boost in Intel Sandy Bridge
1
The need of wide operation range
– Near Threshold Computing: set supply voltage to a
value near to transistor’s threshold voltage (0.4V0.6V)
Intel ISSCC2012
0.28V-1.2V
Future Microprocessor has wide supply voltage
range. Brings challenges to power delivery design
2
Background of Power Delivery Design
• Voltage regulator is key to deliver power at a
specified voltage level
– Linear regulator-LDO
– Switching regulator
• Buck regulator(Off-VR)
• Switch capacitor regulator(On-VR)
Buck Regulator
Switch Capacitor Regulator
Power Conversion Efficiency Characteristics
• VRs are delivering power to wide operational range
cores
High PCE
High PCE
• Off-VR:
– High switching loss
• On-VR:
– Narrow optimal region
• LDO-VR:
– Limited efficiency
Low PCE
Low PCE
Conventional design can’t meet the need of wide voltage range
Contribution
• Explore the design space of wide operational range
power delivery design
• Propose SuperRange, a wide operation range power
delivery scheme
• Present a VR aware power management algorithm to
maximize performance under given power budget
Design space exploration
• Explore three optional design
1. Off-VRs
• Two Off-VR evenly located
2. Off-VR + LDO-VR
• An Off-VR serves as an frontend
3. Off-VR + On-VR
• Off-VR delivers to STV and On-VR to NTV
Option 1：Off-VRs scheme
• Loss in Off-VRs
𝑃𝑐𝑎𝑝 dominants!
𝑃𝑐𝑎𝑝 = 𝐶𝑜 𝑉 2 𝑓
𝑃𝑐𝑎𝑝
𝑖𝑚𝑝𝑙𝑦𝑠 𝑓
Cross 10%
Option 2：LDO-VR scheme
• In LDO-VR
– PCE is limited by the ratio of output
voltage to input voltage
• PCE is lower than 30% when delivering
to NTV region
Option 3：Off-VR + On-VR scheme
• Using Off-VR to deliver to STV region
• Two step voltage conversion
𝑉𝑥 = 𝐷 ∗ 𝑉𝑖𝑛
𝑉𝑜 = 𝑎 𝑉𝑥 − 𝐼𝑜 𝑅𝑖 , 𝑤ℎ𝑒𝑟𝑒𝑅𝑖 ∝ 1/𝑓
• How to decide intermediate voltage 𝑋
1) Fixed intermediate voltage 𝑋
– Off-VR delivers fixed output voltage 2V
– Tuning On-VR params to achieve further
conversion
• PCE of Off-VRs is high
• On-VR couldn’t deliver to all NTV levels at
high PCE
Off-VR + On-VR scheme
2) Using varied intermediate voltage 𝑋
– Off-VR delivers to varied voltage levels
• Duty cycle tuning
– On-VR further step these intermediate values
to 0.4V-0.6V
– Pros:
• On-VR has high PCE(around 80%)
– Cons:
• The PCE of Off-VR remains low because of
small load current
Proposed SuperRange Design
• Multi-phase Off-VR provides an opportunity to
improve load current, thus PCE get improved
– Modern Off-VR can dynamically change number of
working phases
• Decreasing the number of working phases would
increase output ripple
– 1.5uH inductor is big enough
to reduce the ripple with
acceptable area overhead
SuperRange Overview
• Supporting STV
– Voltage conversion to STV is performed by Off-VR
• Supporting NTV
– Two step conversion.
• Off-VR sets to single working phase
• On-VR achieves further conversion(e.g. 3:1)
VR aware power management algorithm
• Maximize performance under
given power budget
– Find optimal core counts and VF
setting
More cores, Low voltage
Few cores, High voltage
• PCE with varying load current
– Although low voltage improve app power efficiency, it
degrades the PCE
Algorithm
• Determine voltage setting candidates
– Computes the total powers when all cores are active at
each voltage level
– Selects the lowest voltage 𝑉𝐿 (𝑃𝐿 > 𝑃𝑏 ) and the highest
voltage 𝑉𝐻 (𝑃𝐿 < 𝑃𝑏 )
• Determine active core count
– Calculate max active core count at voltage 𝑉𝐿 and get
corresponding performance
– Compare the performance with 𝑉𝐻 and make decisions
Experimental Setup
• Target processor characteristics
– Multicore processor consists 16 ALPHA cores which has 9
power state
• (1.2v, 1.9GHz), (1.1v, 1.7GHz), (1.0v, 1.5GHz)… (0.4v, 0.3GHz)
– 32MB LLC, distribute directory-based MESI
– On chip interconnection: mesh + router
• Voltage regulator model
– Single topology (3 to 1) Switch capacitor voltage regulator
– Buck voltage regulator like TI TPS 54912
Power Conversion Efficiency
SuperRange combines the advantages of Off-VR and On-VR and
exhibits high PCE over the entire voltage range
Comparison
• Performance comparison in power-constrait system
SuperRange outperforms LDO scheme by 50% and
Off-VR scheme by 30%
Comparison
• Maximum achievable performance comparison
under shrinking power budget
On average, SuperRange achieve 52% and 170% higher PCE
than Off-VR and LDO-VR scheme.
Conclusion
• Power delivery design for wide operational range is
an important issue
• Explore the optional power delivery design scheme
• The proposed SuperRange scheme achieves high PCE
over the entire operational range
• Propose a VR aware power management algorithm
• Thank You for Your Attention
• Question?