Transcript AMIS2 - CERN Indico

ASIC buck converter
prototypes for LHC upgrades
S.Michelis1,3, C. Azra3, B.Allongue1, G.Blanchot1,
F.Faccio1, C.Fuentes1,2, S.Orlandi1
– PH-ESE
2UTFSM, Valparaiso, Chile
3EPFL, Lausanne
1CERN
Outline

Introduction
 AMIS2
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IHP1
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Features
Pinout
Waveforms
Efficiency
Radiation results
Noise performances
Features
Conclusions
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DC/DC converter requirements:
- Vin= 10-12V
- Vout= 1.8-2.5V
- Switching frequency ~ MHz
due to magnetic field
- Rad-hard design
250Mrd, 2∙1015 n/cm2
Buck converter is the chosen topology:
- high efficiency
- small number of external components
Detector
Power distribution scheme
1.8-2.5V
Power
supply
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DC/DC
10-12V
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First ASIC: AMIS1
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•
•
•
•
FEATURES
VIN and Power Rail Operation from +3.3V to +24V
Includes basic building blocks
External oscillator Programmable from 250kHz to 3MHz
External voltage reference
Vertical HV transistors are used as power switches
PROBLEMS
• Low efficiency due to overlap between gate signals for power mosfet.
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Second ASIC: AMIS2
BTSTR
VRAMP
Rf
Enable freq
D2
Sawtooth
generator
+
-
Enable delay
CBTSR
SW1
driver
IND
L
Vo
R delay
SW2
VDD (for control)
Cout
VDD2 (for drivers)
VF
VSS
S2
SUB
+
Vref
Vref
En_BNGP
ENABLE
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5V
1.8V
2.5V
VI
VF
Vref
SW2
SW1
VI
IPTAT
•
•
•
•
•
•
•
•
FEATURES
VIN and Power Rail Operation from +3.3V to +12V
Internal oscillator fixed at 1Mhz, programmable up to 2.5MHz with external resistor
Internal voltage reference
Programmable delay between gate signals
Integrated feedback loop with bandwidth of 20Khz
Different Vout can be set: 1.2V, 1.8V, 2.5V, 3V, 5V
Lateral HV transistors are used as power switches
Vin
Enable pin
5
AMIS2 circuit details (1)
Gate
SW1
Voltage
Bootstrap circuit needed to drive the high side
switch (SW1) whose source is floating
An external bootstrap capacitor is needed
Cboot > CgSW1 x10
CgSW1=7.5nF (W=0.15m)
Phase
Sw1 on
Vin
Sw1 on
SW1 off
time
Gate
SW1
SW1
Bootstrap
capacitor
L
Vout
Phase
3.3V
Input signal
Cout
SW2
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AMIS2 circuit details (2)
Bandgap provides a constant reference voltage over temperature variations and
radiation effect
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AMIS2 circuit details (3)
The integrated control loop guarantees the stability for input and load variations
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AMIS2 chip layout
•The chip size is 3x3 mm
•The biggest part is reserved to power
transistors
SW1
Drivers
SW2
Vin
+
-
Sawtooth
generator
driver
CONTROL
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Sawtooth
generator
CBTSR
Vo
L
SW2
+
-
Driver logic+
bootstrap
EA Comparator
SW1
Cout
Bandgap
Bandgap
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AMIS2 pinout
Package QFN32
QFN48
D1 D1 D1 D1 D1 D1 D1 D1 INDIND IND IND
POWER
IND
S2
S2
D1 D1 D1 D1 D1 D1 D1
IND
D1 IND
7 mm
5
IND
S2
S2
S2
S2
S2
S2
Vdd2
Vdd2
SUB
SUB
Enable
Enable
IND
IND
S2
S2
IND
IND
S2
S2
IND
IND
S2
BTSTR
IND
S2
BTSTR
OUT
OUT
V25
V5
V25
Enable delay
V18
En_freq
+S2
R_freq
VREF
Vss
Vdd
V18
En_BNDGP
En_freq
R_freq
IPTAT
SW1PAD
SW2PAD
VF
VI
VRAMP
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VREF
Vss
Vdd
CONTROL
R delay
Enable delay
R delay
7 mm
5
S.Michelis CERN/PH
• Several pins for power
transistors.
• Red pins for the control
circuit for testing
• QFN48 for testing
• QFN32 for system level test
10
AMIS2 Waveforms
Waveforms of the input and output voltage, the voltage at the inductor node
(Phase) and the gate signal for SW1.
10
Phase
Gate SW1
Vin
Vout
8
Sw1
on
SW1
off
Sw1
on
V
6
4
2
0
-2
-1.5
-1
-0.5
0
0.5
time (s)
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-6
x 10
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AMIS2 efficiency
•
The measured efficiency goes up to 82%, depending on load current and frequency.
•
Conductive losses are the major contribution of inefficiency.
•
Resistance along the current path is much higher than the one expected for the power transistors
alone. This is due to on-chip routing and bondings.
Vout=2.5V L=538nH
100
90
80
Efficiency
70
60
Iout=1A f=1.5Mhz NO QSW
50
Iout=1A f=1Mhz QSW
40
Iout=0.8A f=1Mhz NO QSW
Iout=2.2A f=1Mhz NO QSW
30
Iout=2.2A f=0.5Mhz NO QSW
20
10
0
7
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7.5
8
8.5
Vin
9
9.5
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Mos resistance
Bonding RBond=80mΩ
Metals RM=50mΩ
Silicon RSi=30mΩ
Package QFN48
Total resistance Rtot=RSi+RM+RBond=160mΩ (more than RSi x 5)
Big impact of bondings and metal routing
QFN32 will reduce a bit the bonding resistance
Final integration maybe with flip chip. It can drastically reduce the conductive losses
AMIS2 Radiation results
The X-ray radiation tests shows a decrease of the efficiency mostly due to the radiation induced
leakage current , compensated by the threshold voltage shift.
Vth (linear)
Efficiency
Efficiency
vsTID
TID
TID
V bandgapvs
vs
0.75
100
82
0.7
0.65
90
1.285
A3
(%)
VEfficiency
bandgap (V)
(%)
Efficiency
Vth (V)
80
80
1.28
70
78
A2
0.55
A1
C1
0.5
0.45
1.275
60
0.4
1.E+02
50
76
1.27
1.E-03
40
Vin=10
Vin=10
1.E+04
1.E+06
Vin=9
Vin=9
Leakage (sat)
1.E+08
TID (rad)
V bandgap
Vin=8
Vin=8
1.E-04
74
1.265
30
Vin=7
Vin=7
Leakage (A)
1.E-05
20
1.26
72
10
1.255
70
0
1.00E+04
Pre
rad
1.00E+04
0.6
1.E-06
A3
1.E-07
A2
1.E-08
A1
1.E-09
C1
1.E-10
1.00E+05
1.00E+05
1.00E+05
1.00E+06
1.00E+06
1.00E+06
1.00E+07
1.00E+08
1.00E+07
1.00E+07
1.00E+08
1.00E+08
TID(rad)
(rad)
TID
TID
(rad)
1.00E+09
1.00E+09
1.00E+09
Annealing Annealing
1.00E+10
1.00E+11
1.E-11
1.00E+10
1.00E+10
1.00E+11
1.00E+11
3 days
7 days
1.E-12
1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
TID (rad)
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Typical application
π filter
Vin
12nH
22uF
22uF
π filter
538nH
12nH
Out
IND
VIN
Vdd
100nF
LIN REGULATOR
3.3V out
1uF
22uF
22uF
Vdd2
Linear
Regulator
Vdd2
1uF
AMIS2
RF=
6.8KOhm
Vdd
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Noise tests with AMIS2
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The AMIS2 power ASIC was mounted on 3 different prototypes:
same schematic, different layouts.

PCB and Coilcraft coils were tested.

Several placements were exercised.

CM, DM and LISN figures were acquired.

The reference setup was used.

Load = 0.9A x 2.5V, Switch frequency = 1.55 MHz.
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AMIS2 Tests: Layout
AMIS2 V1
AMIS2 V2
AMIS2 V3
In/Out on opposite sides
In/Out on corner sides
In/Out on corner sides
Filters on opposite sides
Coil along Y axis
Coil along X axis
Filters close together
Filters further closer
With inductors
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Best noise performances
Best noise performance of AMIS2
CM
DM
Evolution of noise performance of prototype with commercial components
Proto2
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CM
Proto3
CM
S.Michelis CERN/PH
Proto5
CM
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Third ASIC: IHP1
We moved on a 0.25um technology from IHP.
Tests shows that this technology has better performance
•
for radiation tolerance for TID and displacement damage
(see talk of F. Faccio during Power WG)
•
for efficiency (lower on-resistance and capacitance)
A new buck design has been submitted in May 2009 and chip will be back this
week
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FEATURES
VIN and from +2.5V to +12V
Internal oscillator fixed at 2Mhz, programmable
External voltage reference
Adaptive logic for optimum gate delay
External feedback loop with bandwidth of 20Khz
Enable pin
Package QFN48
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Conclusions

AMIS 2 has been tested and it shows good
performances in term of
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Efficiency: up to 82%
Noise: compliant with class A CISPR 11
standards and close to class B limit.
Radiation: after annealing only 2% of efficiency
is lost in the worst case (Vin=10V and
TID=300Mrd)
We have now moved to a 0.25um technology
and first prototype has been delivered this
week
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