2744.Hardware Pace Det Summaryx

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Transcript 2744.Hardware Pace Det Summaryx

Hardware Pace Using Slope
Detection
Tony Calabria
10/22/2012
The Concept
Subhead text here
2
ECG + Pacemaker Signal
Slope Detection
• Frequency components of ECG lie in 0.05 – 150Hz. Frequency of
PACE components reside in >1KHz.
• Monitor for Slope of Pace Signal while ignoring ECG signal slope.
• Need to measure the rate of change of voltage to determine slope:
Differentiator Circuit
– Output signal should not respond to ECG
– Pace Signal should only pass
– Looking for a specific dV/dT
• Pace Spec required to meet:
– 2mV Amplitude Signal
– 100us Period Signal
Alert/Trigger
• Need to trigger an Alert bit when Pace is present
• Using a window comparator, a pulse can be created once the output of
the Differentiator Circuit shows a change outside the preset window.
• Threshold limits set externally depending on amplitude of Differentiator
Output at minimum Pace signal spec requirements (2mV, 100us).
• SR Latch can be used to latch and hold the value of the Comparator
output indicating a Pace Signal has occurred.
• Mandatory that an ECG Signal does not create a response by the
comparator outputs.
Differentiator Circuit
• Looking for specific slope: dV/dT
change
• Duration of slope produces
output amplitude
• R used to set gain
1
fc 
2  R  C
• Frequencies above fc, the circuit
is acting as ordinary inverting
amplifier
Source: http://circuitalley.phpnet.us/circuit3.html
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Window Comparator
• The Differentiator output signal will idle within the window when PACE
is not present
• When PACE appears, the output of the differentiator circuit will toggle,
forcing the voltage outside the limits of the window comparator
– The output to pulse low.
– That low pulse must be latched and held until read back by a uC or GPIO
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SR Latch
• SR Latch output high once Window Comparator outputs low pulse
• Reset line is pulled high
• Latch stays until reset by user.
• Would need to reset with every QRS waveform if wanting to monitor for
pace with each heartbeat
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Proposed Circuit
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Circuit Stability
Subhead text here
10
Differentiator Circuit Analysis
C1 1u
R2 0
C2 10n
C2 used for Op amp Stability
and High Freq gain control
R4 392k
Vo
VCC
Vfb
Vref
V1 2.5
L1 1T
C5 10p
V2 2.5
C4 1T
+
-
+
Vref
+
VCC
C3 10p
VG1
U1 OPA348
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Differentiator Circuit Stability
T 200.00
Rate of Closure =
20dB/Dec
Vo
100.00
Gain (dB)
Vfb
beta
0.00
-100.00
-200.00
200.00
Vo
Phase [deg]
100.00
Vfb
0.00
beta
-100.00
1.00m
100.00
Frequency (Hz)
10.00M
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Time Domain Analysis
VCC
Vref
C2 10n
2mV Amplitude
100us Period
V2 2.5
C1 1u
-
+
+
OPA348
ECGp
R4 392k
R2 0
-
Differentiator out
U1 OPA348
+
+
VECG_block
+
VCC
+
VCC
R1 1M
ECG+PACE
Vpace Pos
V1 2.5
Vref
Model to replace
internal ADS1298
Pace Amplifier
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Time Domain Analysis Cont.
T
2.51
Differentiator out
Set threshold point for
Window Comparator
2.44
2.00m
Pace input pulse
ECG+PACE
-1.00m
2.50
VECG_block
2.50
180.00m
190.00m
Time (s)
200.00m
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Window Comparator Threshold
VCC
VCC
VCC
~ 2.77V
R6 10k
+
R16 100k
R5 8.06k
Vref
+
-
U3 TLV3401
V1 2.5
V2 2.5
V_PACE_OUT
To SR Latch
Differentiator out
VCC
+
U2 TLV3401
+
-
R8 10k
~ 2.48V
R7 10.2k
VCC
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Pace Circuit Design with Values
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Testing
Subhead text here
17
Pace Card Design
• Designed to mate with
ADS1298ECG-FE board
• Top side populated for PACE
OUT 2 and bottom side for
PACE OUT 1
• Requires one 5V supply
• SR Latch Outputs routed to
ADS1298 GPIOs
• Analysis required for circuit
stability
Unstable Design
Differentiator out
Comparator out
SR Latch
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Stable Design
Differentiator out
Comparator out
SR Latch
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Pace Circuit Design with Values
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Pace Circuit Layout
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