Transcript Folie 1 - Indico

Analog Readout Chips – the Status
Ivan Perić, Peter Fischer, Jochen Knopf, Christian Kreidl
Institute for computer engineering
University of Heidelberg
Germany
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DCDBv1
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DCDBv1 chip has been submitted in November 2009, after two months of
design work
The chip is further development of the DCD2 test chip (and the designed
but not submitted DCD3 readout chip)
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DCDBv1 chip
AI
Power
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3.24 mm
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DCDB vs DCD3
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DCD3:
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Technology UMC 180nm with 6 metal layers
144 analog channels
Each channel contains 2 current mode ADCs, regulated cascode as DEPFET signal receiver,
“hand made” data compression digital block
The digital data are serialized and transmitted with 600 Mbits/s by an additional digital block
placed at chip periphery
Each channel contains a bond pad in top metal layer
Channel size is 180 um x 110 um
Chip size 3 “miniasics” – 1.5 mm x 5 mm
Production time 3 months
DCDBv1
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Technology UMC 180nm with 7 metal layers plus solder bumps 
256 analog channels
Each channel contains 2 current mode ADCs (the same as in DCD2), transimpedance
amplifier as DEPFET current receiver and offset correction DAC
The digital data are compressed and serialized in a larger digital block placed on the chip
periphery and operating at 400 MHz. The digital block is synthesized from HDL
Channel size is 200 um x 180 um
Chip size 6 “miniasics” – 3.2 mm x 5 mm determined by the commercial bump bond spacing
of 200 um and DEPFET requirements
Production time 6 months
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DCDBv1 tests
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The first DCDBv1 test results with a “slow” PCB in April 2010
Good noise (2x better than DCD2), reasonable linearity (still 2x worse than
DCD2), maximal operation speed 100MHz due to PCB limitations
We decided to wait for faster PCBs to do more reliable speed
measurements
First test results with SWITCHER_S based hybrid in September 2010
and with SWITCHER_B based hybrid early November 2010
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Summary of the tests
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Despite its complexity, the chip is functional
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Large number of ADCs (512 on a chip)
Novel low voltage pads
New transimpedance amplifier
New technology (seven metal layers and solder bumps)
Use of bump bond adapters and level shifter chips (DCDRO)
New standard cell library
However we have two main problems:
Speed problem:
The chip works well at 100 MHz (250 MHz possible with reduced resolution)
Designed speed is 400MHz (corresponds to 80ns sampling time).
DCD2 works at this speed
Yield problem:
We see too many bad channels – a few per cent (discovered during the test
beam 2010)
And a few minor problems:
Linearity is worse than at DCD2
Input current source seem to be too weak (discovered during the test beam)
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Speed problem
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The speed problem can not be fully reproduced in simulations
However, a few weak points have been identified
Nominal bias voltage for certain delay elements is a bit too low
Resistance of the switches in the ADCs is slightly too high
Simulation gives fine results, but if we had “second order” effects such as
voltage drops, device mismatch on the chip, FET threshold voltage
variations, we could expect the performances we measure
There is an additional hint that the bias voltage for the delay element is too
low
This voltage can be controlled by an on-hip DAC that is normally set to
maximum
When we decrease the DAC setting, the maximum clock frequency DCD
works well at is decreased
The only possibility to check the theories is a new chip
We have submitted a smaller test chip with the fixed ADCs in November
2010
The yield problem have been observed later and has not been addressed
with this submission
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Test chip TC1
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TC1 contains 32 DCD channels.
The chip is implemented using standard 6 metal option, it has bump bond
pads and fits to the existing bump bond adapter and the test system
The chip is not produced with bumps
In this way, the chip is cheaper and the production time is shorter than for a
full scale DCD
The tests can be done using test signals. Additionally DEFET matrix can be
connected, there are 32 analog inputs
Fixes:
The delay bias generator is adjusted to generate higher voltages
The ADC switches have been implemented with low voltage transistors
The bulk of the switch transistors is now biased independently of RefIn
The main sampling switch has been modified to improve linearity
The input current source can drain 2x higher current than in DCDBv1
There is the possibility to measure voltage drops
Voltage regulator for AmpLow has been implemented
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TC1
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Test chip TC1
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TC1 should be available within next few days.
We expect that it operates at 400MHz and that it has linearity as good as
DCD2 because…
We have already two ADC chips based on the same current mode ADCs
that work at 400MHz
DCD2 and SPADIC chip for CBM experiment
SPADIC uses pipeline ADC architecture that is based on identical current
memory cells
There are a few differences between DCDBv1 and these two chips that
could explain the lower speed of DCDBv1
Other than DCDBv1, SPADIC has an independent bias for the bulk of the
switches. TC1 uses the same scheme
In DCD2, the delay bias generator has been based on different DACs and
the voltage range was higher. The maximum DAC setting has been used
for DCD2 too
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Yield issue
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What do we know about the yield issues…
In most of the cases it seems that we have a problem in analog part of a
channel and most precisely in one of the ADCs of a channel
How do we know this?
The broken channel produces a noisy ADC characteristic in at least one part
of the signal range
A problem in digital part (for example a broken via in the signal path) would
most probably cause that the channel generates one single code – no noise
We can slightly change the shape of the noisy ADC characteristic by
changing the bias settings for the ADC
We never see that both ADCs of the same channel are broken. It means
that we have a problem in an ADC and not in the trans-impedance amplifier
More measurements should be done with more statistics
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Yield issue
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Some ideas:
It could be a problem in comparator of the broken ADCs
It could be a broken MiM capacitor
The chip has been submitted with a bit too high top-metal density, which
can be a problem for large chips
The metal density should be decreased for the next chip version, however,
this could lead to increased voltage drops and to other problems. A larger
layout change may be needed
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DCDB – future plans
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Future plans:
We suppose that TC1 will work fine
The next UMC submission is end of March
We can submit the full scale DCD (DCDBv2) with the fixes from the test
chip providing they give good results
We would do only minor changes of the channel layout to meet the density
rules. Larger changes would increase the risk of further errors
The yield problem can be mitigated by adding extra (2) channels
We will improve the testability of the chip by adding the possibility to test the
ADCs on the probe station. We will also add the possibility to monitor
voltage drops
DCDBv2 would be available in November
In the meanwhile, matrix tests can be done with TC1, and DCDBv1 at lower
speed
We will also do probe station tests with DCDBv1 to better understand the
yield problem. A new diploma student could help
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DCDBv2
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Provided everything is going well, we will have the DCDBv2 in early
November. The chip will operate at full speed (350-400MHz) and hopefully
the yield will be improved by adding 2 extra channels
The studies on DCDBv1 will give new hints about the yield issues, so we
will do the necessary changes (for instance layout changes) while waiting
for DCDBv2
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SWITCHER_B
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SWITCHER
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The SWITCHER_B have been tested on a test board (Christian Kreidl) and
on the DEPFET hybrids.
The SWITCHER_B tested by Christian Kreidl works fine. The chip is wire
bonded to the PCB
Many SWITCHER_B chips that were mounted on DEPFET hybrids didn’t
work
It looks at the first sight as a yield problem (?). However, SWITCEHER_B is
a slightly modified version of SWITCHER_S that was produced and
successfully tested in large quantities. SWITCHER_S works excellent. A
yield problem would be a surprise
We have investigated the broken SWITCHER_Bs, and found out that the
slow control (JTAG) parts did not work
Without JTAG, the boundary scan bits are not set - if they are in wrong
state after power up, the input signals (SerIn, Clock, Clear/Gate En) are not
transferred to the main part of the chip. SWITCHER_S does not have slow
control part
We have identified one weak point – the JTAG pads are using extra power
supply (not really necessary) but have protection diodes biased with 3.3V.
The 3.3V supply should always be turned on first, which wasn’t done so at
the beginning
However, fixing of power up sequence didn’t improve the yield
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SWITCHER
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Only the SWITCHER_B chips bonded on the “Clear” side get broken…
There must be some asymmetry between “Clear” and “Gate” side which
leads to the chip failure.
Clear SWITCHER is operated at higher Hi/Lo voltages. (For yield tests, both
SWITCHERs have to be biased equally)
Wire-Bond adapters are different (We should check possible shorts
between bumps and top metal lines on the adapter- and chip side.)
Gate SWITCHER uses different enable signal (GateEn) than Clear
SWITCHER (ClearEn). Different bits in the boundary scan registers are
responsible. (For yield tests, we should check the JTAG functionality for
both Gate and Clear SWITCHER. The JTAG functionality can be tested,
among others, by measuring the Hi supply current for different DAC
settings.)
PCB have been examined many times by Christian Koffmane and Jochen,
there seem to be no problems there.
The problem is still not understood
We will try to measure larger number of SWITCHERs on our probe station.
For simple JTAG tests, only 7 probes are needed
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Summary
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DCDB works which is a big success (it is a large chip with 512 ADCs on it,
etc.)
We have 2x better noise, but 2x reduced speed and 2x worse nonlinearity
than in the case of DCD2
About 2 - 3% of ADCs do not work
We are quite confident that we understand the speed problem
A test chip with the fixed design will be soon available
We will know soon whether the fixes help, if yes, we can submit a new big
DCDB version in March
The yield problem will be investigated by additional measurements. In
worse case, it can be mitigated by adding extra channels
We will keep the DCD2 solution in mind as backup
SWITCHER “yield issues” have to be better understood
They could be a result of damage due to handling and packaging
Probe station measurements will be done
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Future plans
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We are currently testing a new high voltage 180nm AMS/IBM technology. A
SWITCHER chip could be implemented in this technology as well – design
effort is not large
The advantage would be that the chip can be produced with solder bumps
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