Transcript Design Review - Purdue College of Engineering

Krishna Jharjaria TJ Strzelecki Rick Schuman Matt Waldersen
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The Mind Reader is a mobile brain-computer interface.
Computer applications will be presented to the user
through commercially available video glasses.
An EOG and commercially available EEG will be
mounted inside of a common enclosure and will enable
the user to navigate and select various applications.
A dsPIC microcontroller will be used to acquire the
EOG and EEG signals, the EEG signals will be analyzed
by an FPGA and a BeagleBoard XM will control the
virtual reality environment as well as execute all of the
computer applications
1)
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4)
5)
An ability to encode/decode data packets from a
NeuroSky EEG.
An ability for a user to select applications based on
signals from a NeuroSky EEG.
An ability for a user to navigate between different
applications on a display using EOG signals.
An ability for the system to interactively train the
user to effectively operate the device.
An ability to display a live video stream from an
external camera module, and integrate applications
into the video system.
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Considerations
 Signal Processing abilities
 Digital Communication pins
 Optimized for C compiler
 Processing speed
 Resources and reference material
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DSPIC33EP512MU810
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Extensive DSP Library with built in FFT function
4-UART; 4-SPI; 2-I2C
Optimized for C compiler
~53K of RAM
Large online community
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Low Noise
Dual Polarity
Model Available in PSPICE
Multiple Op-Amp Models
Available in DIP and SMD configurations
 With exception of the TLV2211
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High Accuracy
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High Resolution
 19.5 Effective Resolution (Bits RMS)
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Differential input and 2.5V reference output
eliminates need for virtual ground
Integrated Programmable Gain Amplifier
Integrated Digital Filter
Available in both DIP and SMD packages
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Considerations
 Size (Logic Blocks)
 Number of I/O Pins
 Built in Functionality
 Power Consumption
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DLP-HS-FPGA3 USB - FPGA Module
 25,344 Logic Blocks (11,264 slices)
 63 Available user I/O channels
 32 Dedicated Multipliers, libraries for floating point arithmetic
 FPGA module contains: regulators, clock generator, SDRAM, USB
programmer, SPI Flash, compatible with Xilinx ISE WebPack
 FPGA operates on 3.3V, sinks/sources approximately 24mA per I/O pin
BeagleBoard-xM
 1.0 GHz ARM Cortex-A8 Processor
 512 MB RAM
 8 GB microSD HDD
▪ libraries and main program
 4 USB 2.0 Slots
▪ Mouse/Keyboard dev, Webcam
 Expansion Header (Data Transfer)
▪ o SPI
▪ o UART
▪ o I2C
▪ o GPIO
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Modular design
 Maintains separation of digital circuitry and
sensitive analog EOG circuitry
 Enables the EOG circuitry to be placed as close
possible to signal electrodes
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Video glasses will be used in order to ensure
that the video display is directly in front of
the field of view
Light Weight Single Board Computer
BeagleBoard-xM
 Size: 3.35” x 3.45”
 Weight: < 1 lb.
Logitech C310 HD Cam
 1280x720p frame capture
 < 8 oz.
Vuzix Wrap 920
 Twin 640x480p Display
 < 3 oz.
FPGA and Beagle Board
Microcontroller
Interface
EOG inputs
Power
Supply
2 Switch Mode regulators
5V convertor
For FPGA and
Beagle Board
3.3 V convertor
For Microcontroller
11.1V rechargeable Lithium ion Battery
Connected to EOG via SPI
Registered Jack
(RJ11)
Connected to EOG
via SPI
Logic Level convertor
From 5V to 3.3V
In System Programmer
Switch
debouncer
Pin 13 MCRL
Pin 15 PGEC
Pin 16 PGED
Oscillator
PCB mount
Reset
Through hole
Reset Connections
EEG input via UART
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Baud rate = 115200 bps
Specified by the NeuroSky MindWave
4-7hz
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EEG frequency
range 4-7hz
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Array size 512
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Output of the
FFT resides in
RAM
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Inbuilt FFT API:
FFTComplexIP()
BitReverseComplex()
SquareMagnitudeCplx()
Switch
debouncer
Beagle Board
4 I/O for EOG
3 SPI pins for EEG
FPGA Module
Select
button
Logic Level Convertor
From 3.3V to 5V
2x5 bit EOG input
4 bit EOG output
Up, down, left, right
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Main Board
 Multiple Voltages needed
 Power Traces at least 40 mil, signal traces no smaller than 10 mil
 Isolate oscillator
 Physical location of connectors
 Decoupling Capacitors
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EOG Board
 Sensitive analog circuitry
 Distance between electrodes and filtering/amplification
 Physical size of EOG PCB
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Electrooculography measures the signal
given off of corneo-retinal potentials in the
eyes
An EOG circuit consists of an instrumentation
amplifier, amplifiers, low pass filtering and
high pass filtering
A high pass filter is used to eliminate a
naturally occurring DC drift
A low pass filter is used to remove all other
external noise
Instrumentation
Amplifier
 High Input
Impedance
 Includes both a high
pass filter to
eliminate DC drift
and a second order
low pass filter
Sallen-Key 2nd-Order Low Pass Filter
 Eliminates noise from external sources
First Order Low Pass Filter – Amplifier Circuit
 Eliminates noise as well as amplifies the signal
Voltage (V)
Time (s)
Voltage (V)
Time (s)
∆Voltage
Sample Number
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What is an Artificial Neural Network?
 Simplified mathematical model of the human brain
 Utilizes a network of “neurons” to model relationships between inputs
and outputs
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How does a ANN work?
 ANN implement non-linear functions in each neuron
 This function sums weighted input values and passes them through a
non-linear function, usually a Sigmoid function
 This output then propagates to further network layers for the process to
be repeated
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Why use an FPGA implementation
 Highly parallel algorithm, with transistor like output
 Need for quick, complex calculations
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Basics of A Neuron
 Each neuron contains a number of synapses, one for each previous layer
neuron connected
 A synapses will take inputs and multiply it by a predetermined specific
weight
 The weighted values will then be accumulated and funneled into a
nonlinear activation function (Sigmoid Function)
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Hardware Design Considerations
 Need multiple multipliers, one for each synapses (38 multipliers)
▪ Need to condense the size of a neuron
▪ Using control logic and multiple clock cycles we can lower the required
multipliers to a single multiplier per neuron (12 multipliers)
 Implementation of non-linear Sigmoid Function
▪ Look-up Table
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Where we proceed from here
 Training and testing of preliminary ANN using Matlab ANN
toolbox
▪ This will allow the weighted values to be hardcoded into the FPGA
 Design and testing of single neuron in VHDL
 Development of a proven working topology
Tentative HUD Features
•Webcam Live Feed
•EEG Signal Data display
•Home Screen
•3 x 3 application layout
•Concentration to select app
•Programs
•Minimal key input
•Closed apps return to Home
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October 15-19
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 PCB Proof of Parts
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communication
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 Live Feed Visual Software Suite
 EEG ANN prototyped in MATLAB
 PCB assembled
October 22-26
 Simple Software Suite
 Sample EOG circuit
 ADC microcontroller
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Nov 12 – 16
 EOG ANN finished on FPGA
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October 29 – Nov 2
Nov 19 – 23
 Software Test Application
 User Training Application
 Micro to Single-board
communication
 EOG ANN finished in MATLAB
Nov 5 – Nov 9
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Nov 26 – Nov 30
 Troubleshoot
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Dec 3 – Dec 7
 Project Complete