Transcript L5-arch11 - VADA

L5:Lower Power Architecture
Design
1999. 8.2
성균관대학교 조 준 동 교수
http://vada.skku.ac.kr
SungKyunKwan Univ.
VADA Lab.
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Architectural-level Synthesis
• Translate HDL models into sequencing graphs.
• Behavioral-level optimization:
– Optimize abstract models independently from the
implementation parameters.
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Architectural synthesis and optimization:
– Create macroscopic structure:
• data-path and control-unit.
– Consider area and delay information
• Hardware compilation:
– Compile HDL model into sequencing graph.
– Optimize sequencing graph.
– Generate gate-level interconnection for a cell library. of the
implementation.
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Architecture-Level Solutions
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Architecture-Driven Voltage Scaling: Choose more parallel
architecture, Lowering V dd reduces energy, but increase delays
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Regularity: to minimize the power in the control hardware and the
interconnection network.
Modularity: to exploit data locality through distributed processing units, memories and control.
– Spatial locality: an algorithm can be partitioned into natural clusters
based on connectivity
– Temporal locality:average lifetimes of variables (less temporal storage,
probability of future accesses referenced in the recent past).
Few memory references: since references to memories are expensive in
terms of power.
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Precompute physical capacitance of Interconnect and switching
activity (number of bus accesses
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Power Measure of P
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Architecture Trade-off
Reference Data Path
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Parallel Data Path
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Pipelined Data Path
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A Simple Data Path, Result4
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Uni-processor Implementation
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Multi-Processor
Implementation
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Datapath Parallelization
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Memory Parallelization
At first order P= C * f/2 * Vdd2
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VLIW Architecture
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VLIW - cont.
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Compiler takes the responsibility for finding the operations that can be
issued in parallel and creating a single very long instruction containing
these operations. VLIW instruction decoding is easier than superscalar
instruction due to the fixed format and to no instruction dependency.
The fixed format could present more limitations to the combination of
operations.
Intel P6: CISC instructions are combined on chip to provide a set of
micro-operations (i.e., long instruction word) that can be executed in
parallel.
As power becomes a major issue in the design of fast -Pro, the simple
is the better architecture.
VLIW architecture, as they are simpler than N-issue machines, could
be considered as promising architectures to achieve simultaneously
high-speed and low-power.
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Synchronous VS. Asynchronous
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Synchronous system: A signal path starts from a clocked flip- flop
through combinational gates and ends at another clocked flip- flop. The
clock signals do not participate in computation but are required for
synchronizing purposes. With advancement in technology, the systems
tend to get bigger and bigger, and as a result the delay on the clock
wires can no longer be ignored. The problem of clock skew is thus
becoming a bottleneck for many system designers. Many gates switch
unnecessarily just because they are connected to the clock, and not
because they have to process new inputs. The biggest gate is the clock
driver itself which must switch.
Asynchronous system (self-timed): an input signal (request) starts the
computation on a module and an output signal (acknowledge) signifies
the completion of the computation and the availability of the requested
data. Asynchronous systems are potentially response to transitions on
any of their inputs at anytime, since they have no clock with which to
sample their inputs.
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Asynchronous - Cont.
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More difficult to implement, requiring explicit synchronization between
communication blocks without clocks
If the signal feeds directly to conventional gate-level circuitry, invalid
logic levels could propagate throughout the system.
Glitches, which are filtered out by the clock in synchronous designs,
may cause an asynchronous design to malfunction.
Asynchronous designs are not widely used, designers can't find the
supporting design tools and methodologies they need.
DCC Error Corrector of Compact cassette player saves power of 80%
as compared to the synchronous counterpart.
Offers more architectural options/freedom encourages distributed,
localized control offers more freedom to adapt the supply voltage
S. Furber, M. Edwards. “Asynchronous Design Methodologies”.
1993
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Asynchronous design with adaptive scaling of the
supply voltage
(a) Synchronous
system
(b)
Asynchronous
system with
adaptive scaling
of the supply
voltage
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Asynchronous Pipeline
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PIPELINED SELF-TIMED micro P
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Hazard-free Circuits
6% more logics
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